forked from Minki/linux
49148020bc
Merge header files for m68k and m68knommu to the single location:
arch/m68k/include/asm
The majority of this patch was the result of the
script that is included in the changelog below.
The script was originally written by Arnd Bergman and
exten by me to cover a few more files.
When the header files differed the script uses the following:
The original m68k file is named <file>_mm.h [mm for memory manager]
The m68knommu file is named <file>_no.h [no for no memory manager]
The files uses the following include guard:
This include gaurd works as the m68knommu toolchain set
the __uClinux__ symbol - so this should work in userspace too.
Merging the header files for m68k and m68knommu exposes the
(unexpected?) ABI differences thus it is easier to actually
identify these and thus to fix them.
The commit has been build tested with both a m68k and
a m68knommu toolchain - with success.
The commit has also been tested with "make headers_check"
and this patch fixes make headers_check for m68knommu.
The script used:
TARGET=arch/m68k/include/asm
SOURCE=arch/m68knommu/include/asm
INCLUDE="cachectl.h errno.h fcntl.h hwtest.h ioctls.h ipcbuf.h \
linkage.h math-emu.h md.h mman.h movs.h msgbuf.h openprom.h \
oplib.h poll.h posix_types.h resource.h rtc.h sembuf.h shmbuf.h \
shm.h shmparam.h socket.h sockios.h spinlock.h statfs.h stat.h \
termbits.h termios.h tlb.h types.h user.h"
EQUAL="auxvec.h cputime.h device.h emergency-restart.h futex.h \
ioctl.h irq_regs.h kdebug.h local.h mutex.h percpu.h \
sections.h topology.h"
NOMUUFILES="anchor.h bootstd.h coldfire.h commproc.h dbg.h \
elia.h flat.h m5206sim.h m520xsim.h m523xsim.h m5249sim.h \
m5272sim.h m527xsim.h m528xsim.h m5307sim.h m532xsim.h \
m5407sim.h m68360_enet.h m68360.h m68360_pram.h m68360_quicc.h \
m68360_regs.h MC68328.h MC68332.h MC68EZ328.h MC68VZ328.h \
mcfcache.h mcfdma.h mcfmbus.h mcfne.h mcfpci.h mcfpit.h \
mcfsim.h mcfsmc.h mcftimer.h mcfuart.h mcfwdebug.h \
nettel.h quicc_simple.h smp.h"
FILES="atomic.h bitops.h bootinfo.h bug.h bugs.h byteorder.h cache.h \
cacheflush.h checksum.h current.h delay.h div64.h \
dma-mapping.h dma.h elf.h entry.h fb.h fpu.h hardirq.h hw_irq.h io.h \
irq.h kmap_types.h machdep.h mc146818rtc.h mmu.h mmu_context.h \
module.h page.h page_offset.h param.h pci.h pgalloc.h \
pgtable.h processor.h ptrace.h scatterlist.h segment.h \
setup.h sigcontext.h siginfo.h signal.h string.h system.h swab.h \
thread_info.h timex.h tlbflush.h traps.h uaccess.h ucontext.h \
unaligned.h unistd.h"
mergefile() {
BASE=${1%.h}
git mv ${SOURCE}/$1 ${TARGET}/${BASE}_no.h
git mv ${TARGET}/$1 ${TARGET}/${BASE}_mm.h
cat << EOF > ${TARGET}/$1
EOF
git add ${TARGET}/$1
}
set -e
mkdir -p ${TARGET}
git mv include/asm-m68k/* ${TARGET}
rmdir include/asm-m68k
git rm ${SOURCE}/Kbuild
for F in $INCLUDE $EQUAL; do
git rm ${SOURCE}/$F
done
for F in $NOMUUFILES; do
git mv ${SOURCE}/$F ${TARGET}/$F
done
for F in $FILES ; do
mergefile $F
done
rmdir arch/m68knommu/include/asm
rmdir arch/m68knommu/include
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Geert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
363 lines
20 KiB
C
363 lines
20 KiB
C
/***********************************
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* $Id: m68360_quicc.h,v 1.1 2002/03/02 15:01:07 gerg Exp $
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***********************************
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*
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***************************************
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* Definitions of QUICC memory structures
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***************************************
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*/
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#ifndef __M68360_QUICC_H
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#define __M68360_QUICC_H
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/*
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* include registers and
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* parameter ram definitions files
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*/
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#include <asm/m68360_regs.h>
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#include <asm/m68360_pram.h>
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/* Buffer Descriptors */
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typedef struct quicc_bd {
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volatile unsigned short status;
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volatile unsigned short length;
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volatile unsigned char *buf; /* WARNING: This is only true if *char is 32 bits */
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} QUICC_BD;
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#ifdef MOTOROLA_ORIGINAL
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struct user_data {
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/* BASE + 0x000: user data memory */
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volatile unsigned char udata_bd_ucode[0x400]; /*user data bd's Ucode*/
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volatile unsigned char udata_bd[0x200]; /*user data Ucode */
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volatile unsigned char ucode_ext[0x100]; /*Ucode Extention ram */
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volatile unsigned char RESERVED1[0x500]; /* Reserved area */
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};
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#else
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struct user_data {
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/* BASE + 0x000: user data memory */
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volatile unsigned char udata_bd_ucode[0x400]; /* user data, bds, Ucode*/
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volatile unsigned char udata_bd1[0x200]; /* user, bds */
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volatile unsigned char ucode_bd_scratch[0x100]; /* user, bds, ucode scratch */
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volatile unsigned char udata_bd2[0x100]; /* user, bds */
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volatile unsigned char RESERVED1[0x400]; /* Reserved area */
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};
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#endif
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/*
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* internal ram
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*/
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typedef struct quicc {
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union {
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struct quicc32_pram ch_pram_tbl[32]; /* 32*64(bytes) per channel */
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struct user_data u;
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}ch_or_u; /* multipul or user space */
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/* BASE + 0xc00: PARAMETER RAM */
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union {
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struct scc_pram {
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union {
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struct hdlc_pram h;
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struct uart_pram u;
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struct bisync_pram b;
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struct transparent_pram t;
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unsigned char RESERVED66[0x70];
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} pscc; /* scc parameter area (protocol dependent) */
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union {
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struct {
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unsigned char RESERVED70[0x10];
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struct spi_pram spi;
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unsigned char RESERVED72[0x8];
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struct timer_pram timer;
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} timer_spi;
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struct {
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struct idma_pram idma;
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unsigned char RESERVED67[0x4];
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union {
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struct smc_uart_pram u;
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struct smc_trnsp_pram t;
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} psmc;
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} idma_smc;
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} pothers;
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} scc;
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struct ethernet_pram enet_scc;
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struct global_multi_pram m;
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unsigned char pr[0x100];
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} pram[4];
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/* reserved */
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/* BASE + 0x1000: INTERNAL REGISTERS */
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/* SIM */
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volatile unsigned long sim_mcr; /* module configuration reg */
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volatile unsigned short sim_simtr; /* module test register */
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volatile unsigned char RESERVED2[0x2]; /* Reserved area */
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volatile unsigned char sim_avr; /* auto vector reg */
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volatile unsigned char sim_rsr; /* reset status reg */
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volatile unsigned char RESERVED3[0x2]; /* Reserved area */
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volatile unsigned char sim_clkocr; /* CLCO control register */
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volatile unsigned char RESERVED62[0x3]; /* Reserved area */
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volatile unsigned short sim_pllcr; /* PLL control register */
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volatile unsigned char RESERVED63[0x2]; /* Reserved area */
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volatile unsigned short sim_cdvcr; /* Clock devider control register */
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volatile unsigned short sim_pepar; /* Port E pin assignment register */
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volatile unsigned char RESERVED64[0xa]; /* Reserved area */
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volatile unsigned char sim_sypcr; /* system protection control*/
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volatile unsigned char sim_swiv; /* software interrupt vector*/
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volatile unsigned char RESERVED6[0x2]; /* Reserved area */
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volatile unsigned short sim_picr; /* periodic interrupt control reg */
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volatile unsigned char RESERVED7[0x2]; /* Reserved area */
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volatile unsigned short sim_pitr; /* periodic interrupt timing reg */
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volatile unsigned char RESERVED8[0x3]; /* Reserved area */
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volatile unsigned char sim_swsr; /* software service */
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volatile unsigned long sim_bkar; /* breakpoint address register*/
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volatile unsigned long sim_bkcr; /* breakpoint control register*/
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volatile unsigned char RESERVED10[0x8]; /* Reserved area */
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/* MEMC */
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volatile unsigned long memc_gmr; /* Global memory register */
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volatile unsigned short memc_mstat; /* MEMC status register */
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volatile unsigned char RESERVED11[0xa]; /* Reserved area */
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volatile unsigned long memc_br0; /* base register 0 */
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volatile unsigned long memc_or0; /* option register 0 */
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volatile unsigned char RESERVED12[0x8]; /* Reserved area */
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volatile unsigned long memc_br1; /* base register 1 */
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volatile unsigned long memc_or1; /* option register 1 */
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volatile unsigned char RESERVED13[0x8]; /* Reserved area */
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volatile unsigned long memc_br2; /* base register 2 */
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volatile unsigned long memc_or2; /* option register 2 */
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volatile unsigned char RESERVED14[0x8]; /* Reserved area */
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volatile unsigned long memc_br3; /* base register 3 */
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volatile unsigned long memc_or3; /* option register 3 */
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volatile unsigned char RESERVED15[0x8]; /* Reserved area */
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volatile unsigned long memc_br4; /* base register 3 */
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volatile unsigned long memc_or4; /* option register 3 */
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volatile unsigned char RESERVED16[0x8]; /* Reserved area */
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volatile unsigned long memc_br5; /* base register 3 */
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volatile unsigned long memc_or5; /* option register 3 */
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volatile unsigned char RESERVED17[0x8]; /* Reserved area */
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volatile unsigned long memc_br6; /* base register 3 */
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volatile unsigned long memc_or6; /* option register 3 */
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volatile unsigned char RESERVED18[0x8]; /* Reserved area */
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volatile unsigned long memc_br7; /* base register 3 */
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volatile unsigned long memc_or7; /* option register 3 */
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volatile unsigned char RESERVED9[0x28]; /* Reserved area */
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/* TEST */
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volatile unsigned short test_tstmra; /* master shift a */
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volatile unsigned short test_tstmrb; /* master shift b */
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volatile unsigned short test_tstsc; /* shift count */
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volatile unsigned short test_tstrc; /* repetition counter */
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volatile unsigned short test_creg; /* control */
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volatile unsigned short test_dreg; /* destributed register */
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volatile unsigned char RESERVED58[0x404]; /* Reserved area */
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/* IDMA1 */
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volatile unsigned short idma_iccr; /* channel configuration reg*/
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volatile unsigned char RESERVED19[0x2]; /* Reserved area */
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volatile unsigned short idma1_cmr; /* dma mode reg */
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volatile unsigned char RESERVED68[0x2]; /* Reserved area */
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volatile unsigned long idma1_sapr; /* dma source addr ptr */
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volatile unsigned long idma1_dapr; /* dma destination addr ptr */
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volatile unsigned long idma1_bcr; /* dma byte count reg */
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volatile unsigned char idma1_fcr; /* function code reg */
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volatile unsigned char RESERVED20; /* Reserved area */
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volatile unsigned char idma1_cmar; /* channel mask reg */
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volatile unsigned char RESERVED21; /* Reserved area */
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volatile unsigned char idma1_csr; /* channel status reg */
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volatile unsigned char RESERVED22[0x3]; /* Reserved area */
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/* SDMA */
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volatile unsigned char sdma_sdsr; /* status reg */
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volatile unsigned char RESERVED23; /* Reserved area */
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volatile unsigned short sdma_sdcr; /* configuration reg */
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volatile unsigned long sdma_sdar; /* address reg */
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/* IDMA2 */
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volatile unsigned char RESERVED69[0x2]; /* Reserved area */
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volatile unsigned short idma2_cmr; /* dma mode reg */
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volatile unsigned long idma2_sapr; /* dma source addr ptr */
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volatile unsigned long idma2_dapr; /* dma destination addr ptr */
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volatile unsigned long idma2_bcr; /* dma byte count reg */
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volatile unsigned char idma2_fcr; /* function code reg */
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volatile unsigned char RESERVED24; /* Reserved area */
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volatile unsigned char idma2_cmar; /* channel mask reg */
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volatile unsigned char RESERVED25; /* Reserved area */
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volatile unsigned char idma2_csr; /* channel status reg */
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volatile unsigned char RESERVED26[0x7]; /* Reserved area */
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/* Interrupt Controller */
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volatile unsigned long intr_cicr; /* CP interrupt configuration reg*/
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volatile unsigned long intr_cipr; /* CP interrupt pending reg */
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volatile unsigned long intr_cimr; /* CP interrupt mask reg */
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volatile unsigned long intr_cisr; /* CP interrupt in service reg*/
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/* Parallel I/O */
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volatile unsigned short pio_padir; /* port A data direction reg */
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volatile unsigned short pio_papar; /* port A pin assignment reg */
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volatile unsigned short pio_paodr; /* port A open drain reg */
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volatile unsigned short pio_padat; /* port A data register */
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volatile unsigned char RESERVED28[0x8]; /* Reserved area */
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volatile unsigned short pio_pcdir; /* port C data direction reg*/
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volatile unsigned short pio_pcpar; /* port C pin assignment reg*/
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volatile unsigned short pio_pcso; /* port C special options */
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volatile unsigned short pio_pcdat; /* port C data register */
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volatile unsigned short pio_pcint; /* port C interrupt cntrl reg */
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volatile unsigned char RESERVED29[0x16]; /* Reserved area */
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/* Timer */
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volatile unsigned short timer_tgcr; /* timer global configuration reg */
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volatile unsigned char RESERVED30[0xe]; /* Reserved area */
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volatile unsigned short timer_tmr1; /* timer 1 mode reg */
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volatile unsigned short timer_tmr2; /* timer 2 mode reg */
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volatile unsigned short timer_trr1; /* timer 1 referance reg */
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volatile unsigned short timer_trr2; /* timer 2 referance reg */
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volatile unsigned short timer_tcr1; /* timer 1 capture reg */
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volatile unsigned short timer_tcr2; /* timer 2 capture reg */
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volatile unsigned short timer_tcn1; /* timer 1 counter reg */
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volatile unsigned short timer_tcn2; /* timer 2 counter reg */
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volatile unsigned short timer_tmr3; /* timer 3 mode reg */
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volatile unsigned short timer_tmr4; /* timer 4 mode reg */
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volatile unsigned short timer_trr3; /* timer 3 referance reg */
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volatile unsigned short timer_trr4; /* timer 4 referance reg */
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volatile unsigned short timer_tcr3; /* timer 3 capture reg */
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volatile unsigned short timer_tcr4; /* timer 4 capture reg */
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volatile unsigned short timer_tcn3; /* timer 3 counter reg */
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volatile unsigned short timer_tcn4; /* timer 4 counter reg */
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volatile unsigned short timer_ter1; /* timer 1 event reg */
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volatile unsigned short timer_ter2; /* timer 2 event reg */
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volatile unsigned short timer_ter3; /* timer 3 event reg */
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volatile unsigned short timer_ter4; /* timer 4 event reg */
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volatile unsigned char RESERVED34[0x8]; /* Reserved area */
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/* CP */
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volatile unsigned short cp_cr; /* command register */
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volatile unsigned char RESERVED35[0x2]; /* Reserved area */
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volatile unsigned short cp_rccr; /* main configuration reg */
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volatile unsigned char RESERVED37; /* Reserved area */
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volatile unsigned char cp_rmds; /* development support status reg */
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volatile unsigned long cp_rmdr; /* development support control reg */
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volatile unsigned short cp_rctr1; /* ram break register 1 */
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volatile unsigned short cp_rctr2; /* ram break register 2 */
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volatile unsigned short cp_rctr3; /* ram break register 3 */
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volatile unsigned short cp_rctr4; /* ram break register 4 */
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volatile unsigned char RESERVED59[0x2]; /* Reserved area */
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volatile unsigned short cp_rter; /* RISC timers event reg */
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volatile unsigned char RESERVED38[0x2]; /* Reserved area */
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volatile unsigned short cp_rtmr; /* RISC timers mask reg */
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volatile unsigned char RESERVED39[0x14]; /* Reserved area */
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/* BRG */
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union {
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volatile unsigned long l;
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struct {
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volatile unsigned short BRGC_RESERV:14;
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volatile unsigned short rst:1;
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volatile unsigned short en:1;
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volatile unsigned short extc:2;
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volatile unsigned short atb:1;
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volatile unsigned short cd:12;
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volatile unsigned short div16:1;
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} b;
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} brgc[4]; /* BRG1-BRG4 configuration regs*/
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/* SCC registers */
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struct scc_regs {
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union {
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struct {
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/* Low word. */
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volatile unsigned short GSMR_RESERV2:1;
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volatile unsigned short edge:2;
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volatile unsigned short tci:1;
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volatile unsigned short tsnc:2;
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volatile unsigned short rinv:1;
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volatile unsigned short tinv:1;
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volatile unsigned short tpl:3;
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volatile unsigned short tpp:2;
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volatile unsigned short tend:1;
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volatile unsigned short tdcr:2;
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volatile unsigned short rdcr:2;
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volatile unsigned short renc:3;
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volatile unsigned short tenc:3;
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volatile unsigned short diag:2;
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volatile unsigned short enr:1;
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volatile unsigned short ent:1;
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volatile unsigned short mode:4;
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/* High word. */
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volatile unsigned short GSMR_RESERV1:14;
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volatile unsigned short pri:1;
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volatile unsigned short gde:1;
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volatile unsigned short tcrc:2;
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volatile unsigned short revd:1;
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volatile unsigned short trx:1;
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volatile unsigned short ttx:1;
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volatile unsigned short cdp:1;
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volatile unsigned short ctsp:1;
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volatile unsigned short cds:1;
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volatile unsigned short ctss:1;
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volatile unsigned short tfl:1;
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volatile unsigned short rfw:1;
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volatile unsigned short txsy:1;
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volatile unsigned short synl:2;
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volatile unsigned short rtsm:1;
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volatile unsigned short rsyn:1;
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} b;
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struct {
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volatile unsigned long low;
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volatile unsigned long high;
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} w;
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} scc_gsmr; /* SCC general mode reg */
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volatile unsigned short scc_psmr; /* protocol specific mode reg */
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volatile unsigned char RESERVED42[0x2]; /* Reserved area */
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volatile unsigned short scc_todr; /* SCC transmit on demand */
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volatile unsigned short scc_dsr; /* SCC data sync reg */
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volatile unsigned short scc_scce; /* SCC event reg */
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volatile unsigned char RESERVED43[0x2];/* Reserved area */
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volatile unsigned short scc_sccm; /* SCC mask reg */
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volatile unsigned char RESERVED44[0x1];/* Reserved area */
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volatile unsigned char scc_sccs; /* SCC status reg */
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volatile unsigned char RESERVED45[0x8]; /* Reserved area */
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} scc_regs[4];
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/* SMC */
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struct smc_regs {
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volatile unsigned char RESERVED46[0x2]; /* Reserved area */
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volatile unsigned short smc_smcmr; /* SMC mode reg */
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volatile unsigned char RESERVED60[0x2]; /* Reserved area */
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volatile unsigned char smc_smce; /* SMC event reg */
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volatile unsigned char RESERVED47[0x3]; /* Reserved area */
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volatile unsigned char smc_smcm; /* SMC mask reg */
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volatile unsigned char RESERVED48[0x5]; /* Reserved area */
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} smc_regs[2];
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/* SPI */
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volatile unsigned short spi_spmode; /* SPI mode reg */
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volatile unsigned char RESERVED51[0x4]; /* Reserved area */
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volatile unsigned char spi_spie; /* SPI event reg */
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volatile unsigned char RESERVED52[0x3]; /* Reserved area */
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volatile unsigned char spi_spim; /* SPI mask reg */
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volatile unsigned char RESERVED53[0x2]; /* Reserved area */
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volatile unsigned char spi_spcom; /* SPI command reg */
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volatile unsigned char RESERVED54[0x4]; /* Reserved area */
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/* PIP */
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volatile unsigned short pip_pipc; /* pip configuration reg */
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volatile unsigned char RESERVED65[0x2]; /* Reserved area */
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volatile unsigned short pip_ptpr; /* pip timing parameters reg */
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volatile unsigned long pip_pbdir; /* port b data direction reg */
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volatile unsigned long pip_pbpar; /* port b pin assignment reg */
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volatile unsigned long pip_pbodr; /* port b open drain reg */
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volatile unsigned long pip_pbdat; /* port b data reg */
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volatile unsigned char RESERVED71[0x18]; /* Reserved area */
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/* Serial Interface */
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volatile unsigned long si_simode; /* SI mode register */
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volatile unsigned char si_sigmr; /* SI global mode register */
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volatile unsigned char RESERVED55; /* Reserved area */
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volatile unsigned char si_sistr; /* SI status register */
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volatile unsigned char si_sicmr; /* SI command register */
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volatile unsigned char RESERVED56[0x4]; /* Reserved area */
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volatile unsigned long si_sicr; /* SI clock routing */
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volatile unsigned long si_sirp; /* SI ram pointers */
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volatile unsigned char RESERVED57[0xc]; /* Reserved area */
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volatile unsigned short si_siram[0x80]; /* SI routing ram */
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} QUICC;
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#endif
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/*
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* Local variables:
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* c-indent-level: 4
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* c-basic-offset: 4
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* tab-width: 4
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* End:
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*/
|