forked from Minki/linux
3861b2c5d9
Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
310 lines
7.7 KiB
C
310 lines
7.7 KiB
C
/*
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* Broadcom specific AMBA
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* ChipCommon Power Management Unit driver
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*
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* Copyright 2009, Michael Buesch <m@bues.ch>
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* Copyright 2007, Broadcom Corporation
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*
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* Licensed under the GNU/GPL. See COPYING for details.
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*/
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#include "bcma_private.h"
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#include <linux/bcma/bcma.h>
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static u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset)
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{
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bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
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bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);
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return bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
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}
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void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset, u32 value)
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{
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bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
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bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);
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bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, value);
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}
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EXPORT_SYMBOL_GPL(bcma_chipco_pll_write);
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void bcma_chipco_pll_maskset(struct bcma_drv_cc *cc, u32 offset, u32 mask,
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u32 set)
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{
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bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
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bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);
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bcma_cc_maskset32(cc, BCMA_CC_PLLCTL_DATA, mask, set);
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}
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EXPORT_SYMBOL_GPL(bcma_chipco_pll_maskset);
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void bcma_chipco_chipctl_maskset(struct bcma_drv_cc *cc,
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u32 offset, u32 mask, u32 set)
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{
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bcma_cc_write32(cc, BCMA_CC_CHIPCTL_ADDR, offset);
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bcma_cc_read32(cc, BCMA_CC_CHIPCTL_ADDR);
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bcma_cc_maskset32(cc, BCMA_CC_CHIPCTL_DATA, mask, set);
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}
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EXPORT_SYMBOL_GPL(bcma_chipco_chipctl_maskset);
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void bcma_chipco_regctl_maskset(struct bcma_drv_cc *cc, u32 offset, u32 mask,
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u32 set)
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{
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bcma_cc_write32(cc, BCMA_CC_REGCTL_ADDR, offset);
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bcma_cc_read32(cc, BCMA_CC_REGCTL_ADDR);
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bcma_cc_maskset32(cc, BCMA_CC_REGCTL_DATA, mask, set);
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}
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EXPORT_SYMBOL_GPL(bcma_chipco_regctl_maskset);
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static void bcma_pmu_pll_init(struct bcma_drv_cc *cc)
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{
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struct bcma_bus *bus = cc->core->bus;
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switch (bus->chipinfo.id) {
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case 0x4313:
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case 0x4331:
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case 43224:
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case 43225:
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break;
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default:
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pr_err("PLL init unknown for device 0x%04X\n",
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bus->chipinfo.id);
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}
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}
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static void bcma_pmu_resources_init(struct bcma_drv_cc *cc)
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{
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struct bcma_bus *bus = cc->core->bus;
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u32 min_msk = 0, max_msk = 0;
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switch (bus->chipinfo.id) {
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case 0x4313:
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min_msk = 0x200D;
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max_msk = 0xFFFF;
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break;
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case 43224:
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case 43225:
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break;
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default:
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pr_err("PMU resource config unknown for device 0x%04X\n",
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bus->chipinfo.id);
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}
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/* Set the resource masks. */
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if (min_msk)
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bcma_cc_write32(cc, BCMA_CC_PMU_MINRES_MSK, min_msk);
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if (max_msk)
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bcma_cc_write32(cc, BCMA_CC_PMU_MAXRES_MSK, max_msk);
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}
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void bcma_pmu_swreg_init(struct bcma_drv_cc *cc)
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{
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struct bcma_bus *bus = cc->core->bus;
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switch (bus->chipinfo.id) {
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case 0x4313:
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case 0x4331:
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case 43224:
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case 43225:
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break;
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default:
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pr_err("PMU switch/regulators init unknown for device "
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"0x%04X\n", bus->chipinfo.id);
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}
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}
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/* Disable to allow reading SPROM. Don't know the adventages of enabling it. */
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void bcma_chipco_bcm4331_ext_pa_lines_ctl(struct bcma_drv_cc *cc, bool enable)
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{
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struct bcma_bus *bus = cc->core->bus;
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u32 val;
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val = bcma_cc_read32(cc, BCMA_CC_CHIPCTL);
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if (enable) {
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val |= BCMA_CHIPCTL_4331_EXTPA_EN;
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if (bus->chipinfo.pkg == 9 || bus->chipinfo.pkg == 11)
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val |= BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5;
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} else {
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val &= ~BCMA_CHIPCTL_4331_EXTPA_EN;
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val &= ~BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5;
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}
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bcma_cc_write32(cc, BCMA_CC_CHIPCTL, val);
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}
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void bcma_pmu_workarounds(struct bcma_drv_cc *cc)
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{
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struct bcma_bus *bus = cc->core->bus;
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switch (bus->chipinfo.id) {
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case 0x4313:
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bcma_chipco_chipctl_maskset(cc, 0, ~0, 0x7);
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break;
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case 0x4331:
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/* BCM4331 workaround is SPROM-related, we put it in sprom.c */
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break;
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case 43224:
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if (bus->chipinfo.rev == 0) {
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pr_err("Workarounds for 43224 rev 0 not fully "
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"implemented\n");
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bcma_chipco_chipctl_maskset(cc, 0, ~0, 0x00F000F0);
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} else {
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bcma_chipco_chipctl_maskset(cc, 0, ~0, 0xF0);
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}
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break;
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case 43225:
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break;
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default:
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pr_err("Workarounds unknown for device 0x%04X\n",
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bus->chipinfo.id);
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}
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}
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void bcma_pmu_init(struct bcma_drv_cc *cc)
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{
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u32 pmucap;
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pmucap = bcma_cc_read32(cc, BCMA_CC_PMU_CAP);
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cc->pmu.rev = (pmucap & BCMA_CC_PMU_CAP_REVISION);
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pr_debug("Found rev %u PMU (capabilities 0x%08X)\n", cc->pmu.rev,
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pmucap);
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if (cc->pmu.rev == 1)
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bcma_cc_mask32(cc, BCMA_CC_PMU_CTL,
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~BCMA_CC_PMU_CTL_NOILPONW);
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else
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bcma_cc_set32(cc, BCMA_CC_PMU_CTL,
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BCMA_CC_PMU_CTL_NOILPONW);
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if (cc->core->id.id == 0x4329 && cc->core->id.rev == 2)
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pr_err("Fix for 4329b0 bad LPOM state not implemented!\n");
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bcma_pmu_pll_init(cc);
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bcma_pmu_resources_init(cc);
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bcma_pmu_swreg_init(cc);
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bcma_pmu_workarounds(cc);
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}
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u32 bcma_pmu_alp_clock(struct bcma_drv_cc *cc)
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{
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struct bcma_bus *bus = cc->core->bus;
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switch (bus->chipinfo.id) {
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case 0x4716:
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case 0x4748:
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case 47162:
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case 0x4313:
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case 0x5357:
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case 0x4749:
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case 53572:
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/* always 20Mhz */
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return 20000 * 1000;
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case 0x5356:
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case 0x5300:
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/* always 25Mhz */
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return 25000 * 1000;
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default:
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pr_warn("No ALP clock specified for %04X device, "
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"pmu rev. %d, using default %d Hz\n",
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bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_ALP_CLOCK);
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}
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return BCMA_CC_PMU_ALP_CLOCK;
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}
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/* Find the output of the "m" pll divider given pll controls that start with
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* pllreg "pll0" i.e. 12 for main 6 for phy, 0 for misc.
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*/
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static u32 bcma_pmu_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m)
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{
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u32 tmp, div, ndiv, p1, p2, fc;
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struct bcma_bus *bus = cc->core->bus;
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BUG_ON((pll0 & 3) || (pll0 > BCMA_CC_PMU4716_MAINPLL_PLL0));
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BUG_ON(!m || m > 4);
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if (bus->chipinfo.id == 0x5357 || bus->chipinfo.id == 0x4749) {
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/* Detect failure in clock setting */
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tmp = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
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if (tmp & 0x40000)
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return 133 * 1000000;
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}
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tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_P1P2_OFF);
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p1 = (tmp & BCMA_CC_PPL_P1_MASK) >> BCMA_CC_PPL_P1_SHIFT;
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p2 = (tmp & BCMA_CC_PPL_P2_MASK) >> BCMA_CC_PPL_P2_SHIFT;
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tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_M14_OFF);
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div = (tmp >> ((m - 1) * BCMA_CC_PPL_MDIV_WIDTH)) &
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BCMA_CC_PPL_MDIV_MASK;
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tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_NM5_OFF);
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ndiv = (tmp & BCMA_CC_PPL_NDIV_MASK) >> BCMA_CC_PPL_NDIV_SHIFT;
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/* Do calculation in Mhz */
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fc = bcma_pmu_alp_clock(cc) / 1000000;
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fc = (p1 * ndiv * fc) / p2;
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/* Return clock in Hertz */
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return (fc / div) * 1000000;
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}
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/* query bus clock frequency for PMU-enabled chipcommon */
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u32 bcma_pmu_get_clockcontrol(struct bcma_drv_cc *cc)
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{
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struct bcma_bus *bus = cc->core->bus;
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switch (bus->chipinfo.id) {
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case 0x4716:
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case 0x4748:
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case 47162:
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return bcma_pmu_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0,
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BCMA_CC_PMU5_MAINPLL_SSB);
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case 0x5356:
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return bcma_pmu_clock(cc, BCMA_CC_PMU5356_MAINPLL_PLL0,
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BCMA_CC_PMU5_MAINPLL_SSB);
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case 0x5357:
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case 0x4749:
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return bcma_pmu_clock(cc, BCMA_CC_PMU5357_MAINPLL_PLL0,
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BCMA_CC_PMU5_MAINPLL_SSB);
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case 0x5300:
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return bcma_pmu_clock(cc, BCMA_CC_PMU4706_MAINPLL_PLL0,
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BCMA_CC_PMU5_MAINPLL_SSB);
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case 53572:
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return 75000000;
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default:
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pr_warn("No backplane clock specified for %04X device, "
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"pmu rev. %d, using default %d Hz\n",
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bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_HT_CLOCK);
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}
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return BCMA_CC_PMU_HT_CLOCK;
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}
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/* query cpu clock frequency for PMU-enabled chipcommon */
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u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc)
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{
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struct bcma_bus *bus = cc->core->bus;
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if (bus->chipinfo.id == 53572)
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return 300000000;
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if (cc->pmu.rev >= 5) {
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u32 pll;
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switch (bus->chipinfo.id) {
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case 0x5356:
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pll = BCMA_CC_PMU5356_MAINPLL_PLL0;
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break;
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case 0x5357:
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case 0x4749:
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pll = BCMA_CC_PMU5357_MAINPLL_PLL0;
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break;
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default:
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pll = BCMA_CC_PMU4716_MAINPLL_PLL0;
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break;
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}
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/* TODO: if (bus->chipinfo.id == 0x5300)
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return si_4706_pmu_clock(sih, osh, cc, PMU4706_MAINPLL_PLL0, PMU5_MAINPLL_CPU); */
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return bcma_pmu_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU);
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}
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return bcma_pmu_get_clockcontrol(cc);
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}
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