fd6a440ebc
In order to support multi-process debugging, HWS PM4 packet MAP_PROCESS requires an extension of 5 DWORDS to support targeting of per-vmid SPI debug control registers as well as watch points per process. Signed-off-by: Jonathan Kim <jonathan.kim@amd.com> Reviewed-by: Felix Kuehling <felix.kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
94 lines
2.5 KiB
C
94 lines
2.5 KiB
C
/*
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* Copyright 2020 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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/*--------------------MES_MAP_PROCESS (PER DEBUG VMID)--------------------*/
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#ifndef PM4_MES_MAP_PROCESS_PER_DEBUG_VMID_DEFINED
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#define PM4_MES_MAP_PROCESS_PER_DEBUG_VMID_DEFINED
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struct pm4_mes_map_process_aldebaran {
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union {
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union PM4_MES_TYPE_3_HEADER header; /* header */
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uint32_t ordinal1;
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};
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union {
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struct {
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uint32_t pasid:16; /* 0 - 15 */
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uint32_t single_memops:1; /* 16 */
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uint32_t reserved1:1; /* 17 */
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uint32_t debug_vmid:4; /* 18 - 21 */
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uint32_t new_debug:1; /* 22 */
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uint32_t tmz:1; /* 23 */
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uint32_t diq_enable:1; /* 24 */
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uint32_t process_quantum:7; /* 25 - 31 */
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} bitfields2;
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uint32_t ordinal2;
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};
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uint32_t vm_context_page_table_base_addr_lo32;
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uint32_t vm_context_page_table_base_addr_hi32;
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uint32_t sh_mem_bases;
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uint32_t sh_mem_config;
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uint32_t sq_shader_tba_lo;
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uint32_t sq_shader_tba_hi;
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uint32_t sq_shader_tma_lo;
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uint32_t sq_shader_tma_hi;
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uint32_t reserved6;
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uint32_t gds_addr_lo;
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uint32_t gds_addr_hi;
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union {
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struct {
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uint32_t num_gws:7;
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uint32_t sdma_enable:1;
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uint32_t num_oac:4;
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uint32_t gds_size_hi:4;
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uint32_t gds_size:6;
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uint32_t num_queues:10;
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} bitfields14;
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uint32_t ordinal14;
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};
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uint32_t spi_gdbg_per_vmid_cntl;
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uint32_t tcp_watch_cntl[4];
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uint32_t completion_signal_lo;
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uint32_t completion_signal_hi;
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};
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#endif
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