forked from Minki/linux
8b3c8ba3d8
We were expecting to sit on this branch through most of the merge window since
the contents was merged into our tree late, but we ended up sitting on all of
our contents so it can go in with the rest.
The contents here is:
- A large branch of cleanups of the CM/PRM blocks on OMAP.
- A couple of patches plumbing up CM/PRM on OMAP5 and DRA7.
- A branch with DT updates for Freescale i.MX. including some shuffling from
.dts to .dtsi (include) files that causes a little churn.
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Merge tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC late changes from Olof Johansson:
"We were expecting to sit on this branch through most of the merge
window since the contents was merged into our tree late, but we ended
up sitting on all of our contents so it can go in with the rest.
The contents here is:
- a large branch of cleanups of the CM/PRM blocks on OMAP.
- a couple of patches plumbing up CM/PRM on OMAP5 and DRA7.
- a branch with DT updates for Freescale i.MX. including some
shuffling from .dts to .dtsi (include) files that causes a little
churn"
* tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (78 commits)
ARM: OMAP2+: Fix booting with configs that don't have MFD_SYSCON
ARM: OMAP4+: control: add support for initializing control module via DT
ARM: dts: dra7: add minimal l4 bus layout with control module support
ARM: dts: omap5: add minimal l4 bus layout with control module support
ARM: OMAP4+: control: remove support for legacy pad read/write
ARM: OMAP4: display: convert display to use syscon for dsi muxing
ARM: dts: omap4: add minimal l4 bus layout with control module support
ARM: dts: am4372: add minimal l4 bus layout with control module support
ARM: dts: am43xx-epos-evm: fix pinmux node layout
ARM: dts: am33xx: add minimal l4 bus layout with control module support
ARM: dts: omap3: add minimal l4 bus layout with control module support
ARM: dts: omap24xx: add minimal l4 bus layout with control module support
ARM: OMAP2+: control: add syscon support for register accesses
ARM: OMAP2+: id: cache omap_type value
ARM: OMAP2+: control: remove API for getting control module base address
ARM: OMAP2+: clock: add low-level support for regmap
ARM: OMAP4+: PRM: get rid of cpu_is_omap44xx calls from interrupt init
ARM: OMAP4+: PRM: setup prm_features from the PRM init time flags
ARM: OMAP2+: CM: move SoC specific init calls within a generic API
ARM: OMAP4+: PRM: determine prm_device_inst based on DT compatibility
...
689 lines
18 KiB
Plaintext
689 lines
18 KiB
Plaintext
/*
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* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/* AM43x EPOS EVM */
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/dts-v1/;
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#include "am4372.dtsi"
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#include <dt-bindings/pinctrl/am43xx.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/pwm/pwm.h>
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/ {
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model = "TI AM43x EPOS EVM";
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compatible = "ti,am43x-epos-evm","ti,am4372","ti,am43";
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aliases {
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display0 = &lcd0;
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};
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vmmcsd_fixed: fixedregulator-sd {
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compatible = "regulator-fixed";
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regulator-name = "vmmcsd_fixed";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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enable-active-high;
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};
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lcd0: display {
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compatible = "osddisplays,osd057T0559-34ts", "panel-dpi";
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label = "lcd";
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pinctrl-names = "default";
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pinctrl-0 = <&lcd_pins>;
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/*
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* SelLCDorHDMI, LOW to select HDMI. This is not really the
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* panel's enable GPIO, but we don't have HDMI driver support nor
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* support to switch between two displays, so using this gpio as
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* panel's enable should be safe.
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*/
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enable-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
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panel-timing {
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clock-frequency = <33000000>;
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hactive = <800>;
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vactive = <480>;
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hfront-porch = <210>;
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hback-porch = <16>;
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hsync-len = <30>;
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vback-porch = <10>;
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vfront-porch = <22>;
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vsync-len = <13>;
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hsync-active = <0>;
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vsync-active = <0>;
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de-active = <1>;
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pixelclk-active = <1>;
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};
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port {
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lcd_in: endpoint {
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remote-endpoint = <&dpi_out>;
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};
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};
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};
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matrix_keypad: matrix_keypad@0 {
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compatible = "gpio-matrix-keypad";
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debounce-delay-ms = <5>;
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col-scan-delay-us = <2>;
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row-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH /* Bank0, pin12 */
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&gpio0 13 GPIO_ACTIVE_HIGH /* Bank0, pin13 */
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&gpio0 14 GPIO_ACTIVE_HIGH /* Bank0, pin14 */
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&gpio0 15 GPIO_ACTIVE_HIGH>; /* Bank0, pin15 */
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col-gpios = <&gpio3 9 GPIO_ACTIVE_HIGH /* Bank3, pin9 */
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&gpio3 10 GPIO_ACTIVE_HIGH /* Bank3, pin10 */
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&gpio2 18 GPIO_ACTIVE_HIGH /* Bank2, pin18 */
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&gpio2 19 GPIO_ACTIVE_HIGH>; /* Bank2, pin19 */
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linux,keymap = <0x00000201 /* P1 */
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0x01000204 /* P4 */
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0x02000207 /* P7 */
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0x0300020a /* NUMERIC_STAR */
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0x00010202 /* P2 */
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0x01010205 /* P5 */
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0x02010208 /* P8 */
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0x03010200 /* P0 */
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0x00020203 /* P3 */
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0x01020206 /* P6 */
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0x02020209 /* P9 */
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0x0302020b /* NUMERIC_POUND */
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0x00030067 /* UP */
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0x0103006a /* RIGHT */
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0x0203006c /* DOWN */
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0x03030069>; /* LEFT */
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};
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backlight {
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compatible = "pwm-backlight";
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pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
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brightness-levels = <0 51 53 56 62 75 101 152 255>;
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default-brightness-level = <8>;
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};
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};
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&am43xx_pinmux {
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cpsw_default: cpsw_default {
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pinctrl-single,pins = <
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/* Slave 1 */
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0x10c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs */
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0x110 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */
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0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txen.rmii1_txen */
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0x118 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxdv.rmii1_rxdv */
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0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */
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0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */
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0x13c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */
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0x140 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */
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0x144 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_refclk.rmii1_refclk */
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>;
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};
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cpsw_sleep: cpsw_sleep {
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pinctrl-single,pins = <
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/* Slave 1 reset value */
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0x10c (PIN_INPUT_PULLDOWN | MUX_MODE7)
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0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7)
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0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
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0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
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0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
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0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
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0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
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0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
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0x144 (PIN_INPUT_PULLDOWN | MUX_MODE7)
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>;
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};
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davinci_mdio_default: davinci_mdio_default {
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pinctrl-single,pins = <
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/* MDIO */
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0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
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0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
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>;
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};
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davinci_mdio_sleep: davinci_mdio_sleep {
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pinctrl-single,pins = <
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/* MDIO reset value */
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0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
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0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
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>;
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};
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i2c0_pins: pinmux_i2c0_pins {
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pinctrl-single,pins = <
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0x188 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */
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0x18c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */
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>;
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};
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nand_flash_x8: nand_flash_x8 {
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pinctrl-single,pins = <
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0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.SELQSPIorNAND/GPIO */
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0x0 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
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0x4 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
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0x8 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
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0xc (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
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0x10 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
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0x14 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
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0x18 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
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0x1c (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
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0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
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0x74 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpmc_wpn */
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0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
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0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
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0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
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0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
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0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
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>;
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};
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ecap0_pins: backlight_pins {
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pinctrl-single,pins = <
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0x164 MUX_MODE0 /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
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>;
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};
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i2c2_pins: pinmux_i2c2_pins {
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pinctrl-single,pins = <
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0x1c0 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE8) /* i2c2_sda.i2c2_sda */
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0x1c4 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE8) /* i2c2_scl.i2c2_scl */
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>;
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};
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spi0_pins: pinmux_spi0_pins {
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pinctrl-single,pins = <
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0x150 (PIN_INPUT | MUX_MODE0) /* spi0_clk.spi0_clk */
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0x154 (PIN_OUTPUT | MUX_MODE0) /* spi0_d0.spi0_d0 */
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0x158 (PIN_INPUT | MUX_MODE0) /* spi0_d1.spi0_d1 */
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0x15c (PIN_OUTPUT | MUX_MODE0) /* spi0_cs0.spi0_cs0 */
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>;
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};
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spi1_pins: pinmux_spi1_pins {
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pinctrl-single,pins = <
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0x190 (PIN_INPUT | MUX_MODE3) /* mcasp0_aclkx.spi1_clk */
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0x194 (PIN_OUTPUT | MUX_MODE3) /* mcasp0_fsx.spi1_d0 */
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0x198 (PIN_INPUT | MUX_MODE3) /* mcasp0_axr0.spi1_d1 */
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0x19c (PIN_OUTPUT | MUX_MODE3) /* mcasp0_ahclkr.spi1_cs0 */
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>;
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};
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mmc1_pins: pinmux_mmc1_pins {
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pinctrl-single,pins = <
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0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
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>;
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};
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qspi1_default: qspi1_default {
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pinctrl-single,pins = <
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0x7c (PIN_INPUT_PULLUP | MUX_MODE3)
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0x88 (PIN_INPUT_PULLUP | MUX_MODE2)
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0x90 (PIN_INPUT_PULLUP | MUX_MODE3)
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0x94 (PIN_INPUT_PULLUP | MUX_MODE3)
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0x98 (PIN_INPUT_PULLUP | MUX_MODE3)
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0x9c (PIN_INPUT_PULLUP | MUX_MODE3)
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>;
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};
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pixcir_ts_pins: pixcir_ts_pins {
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pinctrl-single,pins = <
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0x44 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_a1.gpio1_17 */
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>;
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};
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hdq_pins: pinmux_hdq_pins {
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pinctrl-single,pins = <
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0x234 (PIN_INPUT_PULLUP | MUX_MODE1) /* cam1_wen.hdq_gpio */
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>;
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};
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dss_pins: dss_pins {
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pinctrl-single,pins = <
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0x020 (PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */
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0x024 (PIN_OUTPUT_PULLUP | MUX_MODE1)
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0x028 (PIN_OUTPUT_PULLUP | MUX_MODE1)
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0x02C (PIN_OUTPUT_PULLUP | MUX_MODE1)
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0x030 (PIN_OUTPUT_PULLUP | MUX_MODE1)
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0x034 (PIN_OUTPUT_PULLUP | MUX_MODE1)
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0x038 (PIN_OUTPUT_PULLUP | MUX_MODE1)
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0x03C (PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 15 -> DSS DATA 16 */
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0x0A0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */
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0x0A4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
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0x0A8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
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0x0AC (PIN_OUTPUT_PULLUP | MUX_MODE0)
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0x0B0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
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0x0B4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
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0x0B8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
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0x0BC (PIN_OUTPUT_PULLUP | MUX_MODE0)
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0x0C0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
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0x0C4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
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0x0C8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
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0x0CC (PIN_OUTPUT_PULLUP | MUX_MODE0)
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0x0D0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
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0x0D4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
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0x0D8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
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0x0DC (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */
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0x0E0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */
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0x0E4 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */
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0x0E8 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */
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0x0EC (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */
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>;
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};
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lcd_pins: lcd_pins {
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pinctrl-single,pins = <
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/* GPMC CLK -> GPIO 2_1 to select LCD / HDMI */
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0x08C (PIN_OUTPUT_PULLUP | MUX_MODE7)
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>;
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};
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vpfe1_pins_default: vpfe1_pins_default {
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pinctrl-single,pins = <
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0x1cc (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data9 mode 0 */
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0x1d0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data8 mode 0 */
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0x1d4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_hd mode 0 */
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0x1d8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_vd mode 0 */
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0x1dc (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_pclk mode 0 */
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0x1e8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data0 mode 0 */
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0x1ec (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data1 mode 0 */
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0x1f0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data2 mode 0 */
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0x1f4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data3 mode 0 */
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0x1f8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data4 mode 0 */
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0x1fc (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data5 mode 0 */
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0x200 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data6 mode 0 */
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0x204 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data7 mode 0 */
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>;
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};
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vpfe1_pins_sleep: vpfe1_pins_sleep {
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pinctrl-single,pins = <
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0x1cc (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
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0x1d0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
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0x1d4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
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0x1d8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
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0x1dc (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
|
|
0x1e8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
|
|
0x1ec (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
|
|
0x1f0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
|
|
0x1f4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
|
|
0x1f8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
|
|
0x1fc (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
|
|
0x200 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
|
|
0x204 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
|
|
>;
|
|
};
|
|
};
|
|
|
|
&mmc1 {
|
|
status = "okay";
|
|
vmmc-supply = <&vmmcsd_fixed>;
|
|
bus-width = <4>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&mmc1_pins>;
|
|
cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
|
|
};
|
|
|
|
&mac {
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&cpsw_default>;
|
|
pinctrl-1 = <&cpsw_sleep>;
|
|
status = "okay";
|
|
};
|
|
|
|
&davinci_mdio {
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&davinci_mdio_default>;
|
|
pinctrl-1 = <&davinci_mdio_sleep>;
|
|
status = "okay";
|
|
};
|
|
|
|
&cpsw_emac0 {
|
|
phy_id = <&davinci_mdio>, <16>;
|
|
phy-mode = "rmii";
|
|
};
|
|
|
|
&cpsw_emac1 {
|
|
phy_id = <&davinci_mdio>, <1>;
|
|
phy-mode = "rmii";
|
|
};
|
|
|
|
&phy_sel {
|
|
rmii-clock-ext;
|
|
};
|
|
|
|
&i2c0 {
|
|
status = "okay";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c0_pins>;
|
|
clock-frequency = <400000>;
|
|
|
|
tps65218: tps65218@24 {
|
|
reg = <0x24>;
|
|
compatible = "ti,tps65218";
|
|
interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* NMIn */
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
|
|
dcdc1: regulator-dcdc1 {
|
|
compatible = "ti,tps65218-dcdc1";
|
|
regulator-name = "vdd_core";
|
|
regulator-min-microvolt = <912000>;
|
|
regulator-max-microvolt = <1144000>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
};
|
|
|
|
dcdc2: regulator-dcdc2 {
|
|
compatible = "ti,tps65218-dcdc2";
|
|
regulator-name = "vdd_mpu";
|
|
regulator-min-microvolt = <912000>;
|
|
regulator-max-microvolt = <1378000>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
};
|
|
|
|
dcdc3: regulator-dcdc3 {
|
|
compatible = "ti,tps65218-dcdc3";
|
|
regulator-name = "vdcdc3";
|
|
regulator-min-microvolt = <1500000>;
|
|
regulator-max-microvolt = <1500000>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
};
|
|
|
|
dcdc5: regulator-dcdc5 {
|
|
compatible = "ti,tps65218-dcdc5";
|
|
regulator-name = "v1_0bat";
|
|
regulator-min-microvolt = <1000000>;
|
|
regulator-max-microvolt = <1000000>;
|
|
};
|
|
|
|
dcdc6: regulator-dcdc6 {
|
|
compatible = "ti,tps65218-dcdc6";
|
|
regulator-name = "v1_8bat";
|
|
regulator-min-microvolt = <1800000>;
|
|
regulator-max-microvolt = <1800000>;
|
|
};
|
|
|
|
ldo1: regulator-ldo1 {
|
|
compatible = "ti,tps65218-ldo1";
|
|
regulator-min-microvolt = <1800000>;
|
|
regulator-max-microvolt = <1800000>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
};
|
|
};
|
|
|
|
at24@50 {
|
|
compatible = "at24,24c256";
|
|
pagesize = <64>;
|
|
reg = <0x50>;
|
|
};
|
|
|
|
pixcir_ts@5c {
|
|
compatible = "pixcir,pixcir_tangoc";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pixcir_ts_pins>;
|
|
reg = <0x5c>;
|
|
interrupt-parent = <&gpio1>;
|
|
interrupts = <17 0>;
|
|
|
|
attb-gpio = <&gpio1 17 GPIO_ACTIVE_HIGH>;
|
|
|
|
touchscreen-size-x = <1024>;
|
|
touchscreen-size-y = <600>;
|
|
};
|
|
};
|
|
|
|
&i2c2 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c2_pins>;
|
|
status = "okay";
|
|
};
|
|
|
|
&gpio0 {
|
|
status = "okay";
|
|
};
|
|
|
|
&gpio1 {
|
|
status = "okay";
|
|
};
|
|
|
|
&gpio2 {
|
|
status = "okay";
|
|
};
|
|
|
|
&gpio3 {
|
|
status = "okay";
|
|
};
|
|
|
|
&elm {
|
|
status = "okay";
|
|
};
|
|
|
|
&gpmc {
|
|
status = "okay"; /* Disable QSPI when enabling GPMC (NAND) */
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&nand_flash_x8>;
|
|
ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */
|
|
nand@0,0 {
|
|
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
|
|
ti,nand-ecc-opt = "bch16";
|
|
ti,elm-id = <&elm>;
|
|
nand-bus-width = <8>;
|
|
gpmc,device-width = <1>;
|
|
gpmc,sync-clk-ps = <0>;
|
|
gpmc,cs-on-ns = <0>;
|
|
gpmc,cs-rd-off-ns = <40>; /* tCEA + tCHZ + 1 */
|
|
gpmc,cs-wr-off-ns = <40>;
|
|
gpmc,adv-on-ns = <0>; /* cs-on-ns */
|
|
gpmc,adv-rd-off-ns = <25>; /* min( tALH + tALS + 1) */
|
|
gpmc,adv-wr-off-ns = <25>; /* min( tALH + tALS + 1) */
|
|
gpmc,we-on-ns = <0>; /* cs-on-ns */
|
|
gpmc,we-off-ns = <20>; /* we-on-time + tWP + 2 */
|
|
gpmc,oe-on-ns = <3>; /* cs-on-ns + tRR + 2 */
|
|
gpmc,oe-off-ns = <30>; /* oe-on-ns + tRP + 2 */
|
|
gpmc,access-ns = <30>; /* tCEA + 4*/
|
|
gpmc,rd-cycle-ns = <40>;
|
|
gpmc,wr-cycle-ns = <40>;
|
|
gpmc,wait-pin = <0>;
|
|
gpmc,bus-turnaround-ns = <0>;
|
|
gpmc,cycle2cycle-delay-ns = <0>;
|
|
gpmc,clk-activation-ns = <0>;
|
|
gpmc,wait-monitoring-ns = <0>;
|
|
gpmc,wr-access-ns = <40>;
|
|
gpmc,wr-data-mux-bus-ns = <0>;
|
|
/* MTD partition table */
|
|
/* All SPL-* partitions are sized to minimal length
|
|
* which can be independently programmable. For
|
|
* NAND flash this is equal to size of erase-block */
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
partition@0 {
|
|
label = "NAND.SPL";
|
|
reg = <0x00000000 0x00040000>;
|
|
};
|
|
partition@1 {
|
|
label = "NAND.SPL.backup1";
|
|
reg = <0x00040000 0x00040000>;
|
|
};
|
|
partition@2 {
|
|
label = "NAND.SPL.backup2";
|
|
reg = <0x00080000 0x00040000>;
|
|
};
|
|
partition@3 {
|
|
label = "NAND.SPL.backup3";
|
|
reg = <0x000C0000 0x00040000>;
|
|
};
|
|
partition@4 {
|
|
label = "NAND.u-boot-spl-os";
|
|
reg = <0x00100000 0x00080000>;
|
|
};
|
|
partition@5 {
|
|
label = "NAND.u-boot";
|
|
reg = <0x00180000 0x00100000>;
|
|
};
|
|
partition@6 {
|
|
label = "NAND.u-boot-env";
|
|
reg = <0x00280000 0x00040000>;
|
|
};
|
|
partition@7 {
|
|
label = "NAND.u-boot-env.backup1";
|
|
reg = <0x002C0000 0x00040000>;
|
|
};
|
|
partition@8 {
|
|
label = "NAND.kernel";
|
|
reg = <0x00300000 0x00700000>;
|
|
};
|
|
partition@9 {
|
|
label = "NAND.file-system";
|
|
reg = <0x00a00000 0x1f600000>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&epwmss0 {
|
|
status = "okay";
|
|
};
|
|
|
|
&tscadc {
|
|
status = "okay";
|
|
|
|
adc {
|
|
ti,adc-channels = <0 1 2 3 4 5 6 7>;
|
|
};
|
|
};
|
|
|
|
&ecap0 {
|
|
status = "okay";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&ecap0_pins>;
|
|
};
|
|
|
|
&spi0 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&spi0_pins>;
|
|
status = "okay";
|
|
};
|
|
|
|
&spi1 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&spi1_pins>;
|
|
status = "okay";
|
|
};
|
|
|
|
&usb2_phy1 {
|
|
status = "okay";
|
|
};
|
|
|
|
&usb1 {
|
|
dr_mode = "peripheral";
|
|
status = "okay";
|
|
};
|
|
|
|
&usb2_phy2 {
|
|
status = "okay";
|
|
};
|
|
|
|
&usb2 {
|
|
dr_mode = "host";
|
|
status = "okay";
|
|
};
|
|
|
|
&qspi {
|
|
status = "disabled"; /* Disable GPMC (NAND) when enabling QSPI */
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&qspi1_default>;
|
|
|
|
spi-max-frequency = <48000000>;
|
|
m25p80@0 {
|
|
compatible = "mx66l51235l";
|
|
spi-max-frequency = <48000000>;
|
|
reg = <0>;
|
|
spi-cpol;
|
|
spi-cpha;
|
|
spi-tx-bus-width = <1>;
|
|
spi-rx-bus-width = <4>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
/* MTD partition table.
|
|
* The ROM checks the first 512KiB
|
|
* for a valid file to boot(XIP).
|
|
*/
|
|
partition@0 {
|
|
label = "QSPI.U_BOOT";
|
|
reg = <0x00000000 0x000080000>;
|
|
};
|
|
partition@1 {
|
|
label = "QSPI.U_BOOT.backup";
|
|
reg = <0x00080000 0x00080000>;
|
|
};
|
|
partition@2 {
|
|
label = "QSPI.U-BOOT-SPL_OS";
|
|
reg = <0x00100000 0x00010000>;
|
|
};
|
|
partition@3 {
|
|
label = "QSPI.U_BOOT_ENV";
|
|
reg = <0x00110000 0x00010000>;
|
|
};
|
|
partition@4 {
|
|
label = "QSPI.U-BOOT-ENV.backup";
|
|
reg = <0x00120000 0x00010000>;
|
|
};
|
|
partition@5 {
|
|
label = "QSPI.KERNEL";
|
|
reg = <0x00130000 0x0800000>;
|
|
};
|
|
partition@6 {
|
|
label = "QSPI.FILESYSTEM";
|
|
reg = <0x00930000 0x36D0000>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&hdq {
|
|
status = "okay";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&hdq_pins>;
|
|
};
|
|
|
|
&dss {
|
|
status = "ok";
|
|
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&dss_pins>;
|
|
|
|
port {
|
|
dpi_out: endpoint@0 {
|
|
remote-endpoint = <&lcd_in>;
|
|
data-lines = <24>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&vpfe1 {
|
|
status = "okay";
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&vpfe1_pins_default>;
|
|
pinctrl-1 = <&vpfe1_pins_sleep>;
|
|
|
|
port {
|
|
vpfe1_ep: endpoint {
|
|
/* remote-endpoint = <&sensor>; add once we have it */
|
|
ti,am437x-vpfe-interface = <0>;
|
|
bus-width = <8>;
|
|
hsync-active = <0>;
|
|
vsync-active = <0>;
|
|
};
|
|
};
|
|
};
|