forked from Minki/linux
ed2ca6ee4b
* A bunch of new board additions, imx6sl-evk, vf610-twr, imx53-tx53,
imx53-m53evk and imx27-phytec-phycore
* Various pinctrl setting updates and additions
* Enable various on board peripherals, usb, audio, nor, display etc.
* Configure L2 cache data and tag latency from device tree
* Add imx-weim bus driver
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Merge tag 'imx-dt-3.11' of git://git.linaro.org/people/shawnguo/linux-2.6 into next/dt
From Shawn Guo:
imx device tree changes for 3.11:
* A bunch of new board additions, imx6sl-evk, vf610-twr, imx53-tx53,
imx53-m53evk and imx27-phytec-phycore
* Various pinctrl setting updates and additions
* Enable various on board peripherals, usb, audio, nor, display etc.
* Configure L2 cache data and tag latency from device tree
* Add imx-weim bus driver
* tag 'imx-dt-3.11' of git://git.linaro.org/people/shawnguo/linux-2.6: (82 commits)
ARM: dts: imx27: Add VPU devicetree node
ARM: mxc: fix gpio-ranges for VF610
ARM: dtsi: imx6qdl-sabresd: Enable WM8962 audio support
ARM: dtsi: imx6qdl-sabresd: Enable SSI2 and AUDMUX
ARM: dtsi: imx6qdl-sabresd: Add WM8962 CODEC support
ARM: dtsi: imx6qdl-sabresd: add a fixed regulator for WM8962
ARM: dtsi: imx6dl: Add a pinctrl for AUDMUX
ARM: dtsi: imx6q/imx6dl: Add a pinctrl for I2C1
ARM: dts: imx6qdl-sabresd: add clko1 iomux configuration
ARM: dts: Phytec imx6q pfla02 and pbab01 support
ARM: dts: imx6q: Add pinctrl for usdhc2 and enet
ARM: dts: imx27-phytec-phycore-rdk: Add MTD name for NOR flash
ARM: dts: imx27-phytec-phycore-rdk: Add SDHC support
ARM: dts: i.MX27: Add SDHC devicetree nodes
ARM: dts: i.MX27: Add DMA devicetree node
ARM: dts: imx6qdl-sabreauto: enable the WEIM NOR
ARM: dts: imx6dl: add pinctrls for WEIM NOR
ARM: dts: imx6q: add pinctrls for WEIM NOR
ARM: dts: imx6qdl: add more information for WEIM
ARM: dts: imx6q{dl}: fix the pin conflict between SPI and WEIM
...
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
459 lines
13 KiB
Plaintext
459 lines
13 KiB
Plaintext
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/*
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* Copyright 2013 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include "imx6qdl.dtsi"
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#include "imx6q-pinfunc.h"
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "arm,cortex-a9";
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device_type = "cpu";
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reg = <0>;
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next-level-cache = <&L2>;
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operating-points = <
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/* kHz uV */
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1200000 1275000
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996000 1250000
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792000 1150000
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396000 950000
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>;
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clock-latency = <61036>; /* two CLK32 periods */
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clocks = <&clks 104>, <&clks 6>, <&clks 16>,
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<&clks 17>, <&clks 170>;
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clock-names = "arm", "pll2_pfd2_396m", "step",
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"pll1_sw", "pll1_sys";
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arm-supply = <®_arm>;
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pu-supply = <®_pu>;
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soc-supply = <®_soc>;
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};
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cpu@1 {
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compatible = "arm,cortex-a9";
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device_type = "cpu";
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reg = <1>;
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next-level-cache = <&L2>;
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};
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cpu@2 {
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compatible = "arm,cortex-a9";
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device_type = "cpu";
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reg = <2>;
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next-level-cache = <&L2>;
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};
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cpu@3 {
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compatible = "arm,cortex-a9";
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device_type = "cpu";
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reg = <3>;
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next-level-cache = <&L2>;
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};
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};
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soc {
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aips-bus@02000000 { /* AIPS1 */
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spba-bus@02000000 {
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ecspi5: ecspi@02018000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
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reg = <0x02018000 0x4000>;
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interrupts = <0 35 0x04>;
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clocks = <&clks 116>, <&clks 116>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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};
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iomuxc: iomuxc@020e0000 {
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compatible = "fsl,imx6q-iomuxc";
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reg = <0x020e0000 0x4000>;
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/* shared pinctrl settings */
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audmux {
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pinctrl_audmux_1: audmux-1 {
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fsl,pins = <
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MX6Q_PAD_SD2_DAT0__AUD4_RXD 0x80000000
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MX6Q_PAD_SD2_DAT3__AUD4_TXC 0x80000000
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MX6Q_PAD_SD2_DAT2__AUD4_TXD 0x80000000
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MX6Q_PAD_SD2_DAT1__AUD4_TXFS 0x80000000
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>;
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};
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pinctrl_audmux_2: audmux-2 {
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fsl,pins = <
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MX6Q_PAD_CSI0_DAT7__AUD3_RXD 0x80000000
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MX6Q_PAD_CSI0_DAT4__AUD3_TXC 0x80000000
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MX6Q_PAD_CSI0_DAT5__AUD3_TXD 0x80000000
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MX6Q_PAD_CSI0_DAT6__AUD3_TXFS 0x80000000
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>;
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};
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};
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ecspi1 {
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pinctrl_ecspi1_1: ecspi1grp-1 {
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fsl,pins = <
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MX6Q_PAD_EIM_D17__ECSPI1_MISO 0x100b1
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MX6Q_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
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MX6Q_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
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>;
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};
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};
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ecspi3 {
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pinctrl_ecspi3_1: ecspi3grp-1 {
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fsl,pins = <
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MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
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MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
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MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
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>;
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};
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};
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enet {
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pinctrl_enet_1: enetgrp-1 {
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fsl,pins = <
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MX6Q_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
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MX6Q_PAD_ENET_MDC__ENET_MDC 0x1b0b0
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MX6Q_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
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MX6Q_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
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MX6Q_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
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MX6Q_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
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MX6Q_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
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MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
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MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
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MX6Q_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
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MX6Q_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
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MX6Q_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
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MX6Q_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
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MX6Q_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
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MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
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MX6Q_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
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>;
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};
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pinctrl_enet_2: enetgrp-2 {
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fsl,pins = <
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MX6Q_PAD_KEY_COL1__ENET_MDIO 0x1b0b0
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MX6Q_PAD_KEY_COL2__ENET_MDC 0x1b0b0
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MX6Q_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
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MX6Q_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
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MX6Q_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
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MX6Q_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
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MX6Q_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
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MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
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MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
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MX6Q_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
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MX6Q_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
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MX6Q_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
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MX6Q_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
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MX6Q_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
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MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
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>;
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};
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pinctrl_enet_3: enetgrp-3 {
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fsl,pins = <
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MX6Q_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
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MX6Q_PAD_ENET_MDC__ENET_MDC 0x1b0b0
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MX6Q_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
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MX6Q_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
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MX6Q_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
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MX6Q_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
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MX6Q_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
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MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
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MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
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MX6Q_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
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MX6Q_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
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MX6Q_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
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MX6Q_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
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MX6Q_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
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MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
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MX6Q_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
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>;
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};
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};
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gpmi-nand {
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pinctrl_gpmi_nand_1: gpmi-nand-1 {
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fsl,pins = <
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MX6Q_PAD_NANDF_CLE__NAND_CLE 0xb0b1
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MX6Q_PAD_NANDF_ALE__NAND_ALE 0xb0b1
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MX6Q_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
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MX6Q_PAD_NANDF_RB0__NAND_READY_B 0xb000
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MX6Q_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
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MX6Q_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
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MX6Q_PAD_SD4_CMD__NAND_RE_B 0xb0b1
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MX6Q_PAD_SD4_CLK__NAND_WE_B 0xb0b1
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MX6Q_PAD_NANDF_D0__NAND_DATA00 0xb0b1
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MX6Q_PAD_NANDF_D1__NAND_DATA01 0xb0b1
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MX6Q_PAD_NANDF_D2__NAND_DATA02 0xb0b1
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MX6Q_PAD_NANDF_D3__NAND_DATA03 0xb0b1
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MX6Q_PAD_NANDF_D4__NAND_DATA04 0xb0b1
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MX6Q_PAD_NANDF_D5__NAND_DATA05 0xb0b1
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MX6Q_PAD_NANDF_D6__NAND_DATA06 0xb0b1
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MX6Q_PAD_NANDF_D7__NAND_DATA07 0xb0b1
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MX6Q_PAD_SD4_DAT0__NAND_DQS 0x00b1
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>;
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};
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};
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i2c1 {
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pinctrl_i2c1_1: i2c1grp-1 {
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fsl,pins = <
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MX6Q_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
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MX6Q_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
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>;
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};
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pinctrl_i2c1_2: i2c1grp-2 {
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fsl,pins = <
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MX6Q_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
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MX6Q_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
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>;
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};
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};
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i2c2 {
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pinctrl_i2c2_1: i2c2grp-1 {
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fsl,pins = <
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MX6Q_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
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MX6Q_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
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>;
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};
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};
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i2c3 {
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pinctrl_i2c3_1: i2c3grp-1 {
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fsl,pins = <
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MX6Q_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
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MX6Q_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
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>;
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};
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};
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uart1 {
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pinctrl_uart1_1: uart1grp-1 {
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fsl,pins = <
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MX6Q_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
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MX6Q_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
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>;
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};
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};
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uart2 {
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pinctrl_uart2_1: uart2grp-1 {
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fsl,pins = <
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MX6Q_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
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MX6Q_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
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>;
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};
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};
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uart4 {
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pinctrl_uart4_1: uart4grp-1 {
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fsl,pins = <
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MX6Q_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
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MX6Q_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
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>;
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};
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};
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usbotg {
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pinctrl_usbotg_1: usbotggrp-1 {
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fsl,pins = <
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MX6Q_PAD_GPIO_1__USB_OTG_ID 0x17059
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>;
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};
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pinctrl_usbotg_2: usbotggrp-2 {
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fsl,pins = <
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MX6Q_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
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>;
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};
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};
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usdhc2 {
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pinctrl_usdhc2_1: usdhc2grp-1 {
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fsl,pins = <
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MX6Q_PAD_SD2_CMD__SD2_CMD 0x17059
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MX6Q_PAD_SD2_CLK__SD2_CLK 0x10059
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MX6Q_PAD_SD2_DAT0__SD2_DATA0 0x17059
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MX6Q_PAD_SD2_DAT1__SD2_DATA1 0x17059
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MX6Q_PAD_SD2_DAT2__SD2_DATA2 0x17059
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MX6Q_PAD_SD2_DAT3__SD2_DATA3 0x17059
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MX6Q_PAD_NANDF_D4__SD2_DATA4 0x17059
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MX6Q_PAD_NANDF_D5__SD2_DATA5 0x17059
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MX6Q_PAD_NANDF_D6__SD2_DATA6 0x17059
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MX6Q_PAD_NANDF_D7__SD2_DATA7 0x17059
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>;
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};
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pinctrl_usdhc2_2: usdhc2grp-2 {
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fsl,pins = <
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MX6Q_PAD_SD2_CMD__SD2_CMD 0x17059
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MX6Q_PAD_SD2_CLK__SD2_CLK 0x10059
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MX6Q_PAD_SD2_DAT0__SD2_DATA0 0x17059
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MX6Q_PAD_SD2_DAT1__SD2_DATA1 0x17059
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MX6Q_PAD_SD2_DAT2__SD2_DATA2 0x17059
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MX6Q_PAD_SD2_DAT3__SD2_DATA3 0x17059
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>;
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};
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};
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usdhc3 {
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pinctrl_usdhc3_1: usdhc3grp-1 {
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fsl,pins = <
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MX6Q_PAD_SD3_CMD__SD3_CMD 0x17059
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MX6Q_PAD_SD3_CLK__SD3_CLK 0x10059
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MX6Q_PAD_SD3_DAT0__SD3_DATA0 0x17059
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MX6Q_PAD_SD3_DAT1__SD3_DATA1 0x17059
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MX6Q_PAD_SD3_DAT2__SD3_DATA2 0x17059
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MX6Q_PAD_SD3_DAT3__SD3_DATA3 0x17059
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MX6Q_PAD_SD3_DAT4__SD3_DATA4 0x17059
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MX6Q_PAD_SD3_DAT5__SD3_DATA5 0x17059
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MX6Q_PAD_SD3_DAT6__SD3_DATA6 0x17059
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MX6Q_PAD_SD3_DAT7__SD3_DATA7 0x17059
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>;
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};
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pinctrl_usdhc3_2: usdhc3grp-2 {
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fsl,pins = <
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MX6Q_PAD_SD3_CMD__SD3_CMD 0x17059
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MX6Q_PAD_SD3_CLK__SD3_CLK 0x10059
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MX6Q_PAD_SD3_DAT0__SD3_DATA0 0x17059
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MX6Q_PAD_SD3_DAT1__SD3_DATA1 0x17059
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MX6Q_PAD_SD3_DAT2__SD3_DATA2 0x17059
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MX6Q_PAD_SD3_DAT3__SD3_DATA3 0x17059
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>;
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};
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};
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usdhc4 {
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pinctrl_usdhc4_1: usdhc4grp-1 {
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fsl,pins = <
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MX6Q_PAD_SD4_CMD__SD4_CMD 0x17059
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MX6Q_PAD_SD4_CLK__SD4_CLK 0x10059
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MX6Q_PAD_SD4_DAT0__SD4_DATA0 0x17059
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MX6Q_PAD_SD4_DAT1__SD4_DATA1 0x17059
|
|
MX6Q_PAD_SD4_DAT2__SD4_DATA2 0x17059
|
|
MX6Q_PAD_SD4_DAT3__SD4_DATA3 0x17059
|
|
MX6Q_PAD_SD4_DAT4__SD4_DATA4 0x17059
|
|
MX6Q_PAD_SD4_DAT5__SD4_DATA5 0x17059
|
|
MX6Q_PAD_SD4_DAT6__SD4_DATA6 0x17059
|
|
MX6Q_PAD_SD4_DAT7__SD4_DATA7 0x17059
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc4_2: usdhc4grp-2 {
|
|
fsl,pins = <
|
|
MX6Q_PAD_SD4_CMD__SD4_CMD 0x17059
|
|
MX6Q_PAD_SD4_CLK__SD4_CLK 0x10059
|
|
MX6Q_PAD_SD4_DAT0__SD4_DATA0 0x17059
|
|
MX6Q_PAD_SD4_DAT1__SD4_DATA1 0x17059
|
|
MX6Q_PAD_SD4_DAT2__SD4_DATA2 0x17059
|
|
MX6Q_PAD_SD4_DAT3__SD4_DATA3 0x17059
|
|
>;
|
|
};
|
|
};
|
|
|
|
weim {
|
|
pinctrl_weim_cs0_1: weim_cs0grp-1 {
|
|
fsl,pins = <
|
|
MX6Q_PAD_EIM_CS0__EIM_CS0_B 0xb0b1
|
|
>;
|
|
};
|
|
|
|
pinctrl_weim_nor_1: weimnorgrp-1 {
|
|
fsl,pins = <
|
|
MX6Q_PAD_EIM_OE__EIM_OE_B 0xb0b1
|
|
MX6Q_PAD_EIM_RW__EIM_RW 0xb0b1
|
|
MX6Q_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
|
|
/* data */
|
|
MX6Q_PAD_EIM_D16__EIM_DATA16 0x1b0b0
|
|
MX6Q_PAD_EIM_D17__EIM_DATA17 0x1b0b0
|
|
MX6Q_PAD_EIM_D18__EIM_DATA18 0x1b0b0
|
|
MX6Q_PAD_EIM_D19__EIM_DATA19 0x1b0b0
|
|
MX6Q_PAD_EIM_D20__EIM_DATA20 0x1b0b0
|
|
MX6Q_PAD_EIM_D21__EIM_DATA21 0x1b0b0
|
|
MX6Q_PAD_EIM_D22__EIM_DATA22 0x1b0b0
|
|
MX6Q_PAD_EIM_D23__EIM_DATA23 0x1b0b0
|
|
MX6Q_PAD_EIM_D24__EIM_DATA24 0x1b0b0
|
|
MX6Q_PAD_EIM_D25__EIM_DATA25 0x1b0b0
|
|
MX6Q_PAD_EIM_D26__EIM_DATA26 0x1b0b0
|
|
MX6Q_PAD_EIM_D27__EIM_DATA27 0x1b0b0
|
|
MX6Q_PAD_EIM_D28__EIM_DATA28 0x1b0b0
|
|
MX6Q_PAD_EIM_D29__EIM_DATA29 0x1b0b0
|
|
MX6Q_PAD_EIM_D30__EIM_DATA30 0x1b0b0
|
|
MX6Q_PAD_EIM_D31__EIM_DATA31 0x1b0b0
|
|
/* address */
|
|
MX6Q_PAD_EIM_A23__EIM_ADDR23 0xb0b1
|
|
MX6Q_PAD_EIM_A22__EIM_ADDR22 0xb0b1
|
|
MX6Q_PAD_EIM_A21__EIM_ADDR21 0xb0b1
|
|
MX6Q_PAD_EIM_A20__EIM_ADDR20 0xb0b1
|
|
MX6Q_PAD_EIM_A19__EIM_ADDR19 0xb0b1
|
|
MX6Q_PAD_EIM_A18__EIM_ADDR18 0xb0b1
|
|
MX6Q_PAD_EIM_A17__EIM_ADDR17 0xb0b1
|
|
MX6Q_PAD_EIM_A16__EIM_ADDR16 0xb0b1
|
|
MX6Q_PAD_EIM_DA15__EIM_AD15 0xb0b1
|
|
MX6Q_PAD_EIM_DA14__EIM_AD14 0xb0b1
|
|
MX6Q_PAD_EIM_DA13__EIM_AD13 0xb0b1
|
|
MX6Q_PAD_EIM_DA12__EIM_AD12 0xb0b1
|
|
MX6Q_PAD_EIM_DA11__EIM_AD11 0xb0b1
|
|
MX6Q_PAD_EIM_DA10__EIM_AD10 0xb0b1
|
|
MX6Q_PAD_EIM_DA9__EIM_AD09 0xb0b1
|
|
MX6Q_PAD_EIM_DA8__EIM_AD08 0xb0b1
|
|
MX6Q_PAD_EIM_DA7__EIM_AD07 0xb0b1
|
|
MX6Q_PAD_EIM_DA6__EIM_AD06 0xb0b1
|
|
MX6Q_PAD_EIM_DA5__EIM_AD05 0xb0b1
|
|
MX6Q_PAD_EIM_DA4__EIM_AD04 0xb0b1
|
|
MX6Q_PAD_EIM_DA3__EIM_AD03 0xb0b1
|
|
MX6Q_PAD_EIM_DA2__EIM_AD02 0xb0b1
|
|
MX6Q_PAD_EIM_DA1__EIM_AD01 0xb0b1
|
|
MX6Q_PAD_EIM_DA0__EIM_AD00 0xb0b1
|
|
>;
|
|
};
|
|
|
|
};
|
|
};
|
|
};
|
|
|
|
ipu2: ipu@02800000 {
|
|
#crtc-cells = <1>;
|
|
compatible = "fsl,imx6q-ipu";
|
|
reg = <0x02800000 0x400000>;
|
|
interrupts = <0 8 0x4 0 7 0x4>;
|
|
clocks = <&clks 133>, <&clks 134>, <&clks 137>;
|
|
clock-names = "bus", "di0", "di1";
|
|
resets = <&src 4>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&ldb {
|
|
clocks = <&clks 33>, <&clks 34>,
|
|
<&clks 39>, <&clks 40>, <&clks 41>, <&clks 42>,
|
|
<&clks 135>, <&clks 136>;
|
|
clock-names = "di0_pll", "di1_pll",
|
|
"di0_sel", "di1_sel", "di2_sel", "di3_sel",
|
|
"di0", "di1";
|
|
|
|
lvds-channel@0 {
|
|
crtcs = <&ipu1 0>, <&ipu1 1>, <&ipu2 0>, <&ipu2 1>;
|
|
};
|
|
|
|
lvds-channel@1 {
|
|
crtcs = <&ipu1 0>, <&ipu1 1>, <&ipu2 0>, <&ipu2 1>;
|
|
};
|
|
};
|