forked from Minki/linux
c2714334b9
This is a branch with updates for Marvell's mvebu/kirkwood platforms. They came in late-ish, and were heavily interdependent such that it didn't make sense to split them up across the cross-platform topic branches. So here they are (for the second release in a row) in a branch on their own. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAABAgAGBQJQy5i9AAoJEIwa5zzehBx3ZskP/2wxjbwEaNdnR+7j8595bTaa GYq8qJ4lUCOKmSqp3bQkg/Plm2D88p78BO5qTm2io527gl10HemzCiGaejclujIw sDFZPAE8K0Z8p0gQcBNlRZNuI3J1N6IKRqYH5SIJ2vWmBMfO7nKRR9nmTiDpm5bx IcuKX2u/mhyXWN+F0EcHqcupH1K+mdzyGdIQk80Tyqni+UTN+pd0efLM6WL4SFJM 5fj64dDFpVDA8t+O2Avz8p+lx07vkSy2wIXWt7Ik9BVtsyZQecn+9lpl8FvcrSK/ MgL3QO4kqDpJDs88M7DJURU1/EdsWZc32M63avctaWnGWItQAbOJYBDmZTlng08x ZGrKOgf/I6le7wEpnzdag9ymI/rAL8I0755FkfXxf1R7/X40b+t8/61J/ddOKTDs 1sTVt+eKyyIMWle4V4zENa03goVBApCIEXcmnuFisFNbBY6azV31inJEp/3PvpgE GeMBfxBDkvn+03LkRFcZlhTeDsNTdctD+sfgrNPaQf5bZGIvEz87vgfNTIiaU3GA Vd5aiainVDQgmpoFfRG6391gdFlF2l9d67LoG4ClCjn4WL+UxcTRuzBW/liORpUO E7CwMHtPq6eoGKywiKMFRzY2QRIKZRkxrC2PCJ/1V9mbIGwgaD/3BQ2/czwrnc8q 1gnxWx8E5SKEGcDJXD+6 =7luC -----END PGP SIGNATURE----- Merge tag 'mvebu' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC updates for Marvell mvebu/kirkwood from Olof Johansson: "This is a branch with updates for Marvell's mvebu/kirkwood platforms. They came in late-ish, and were heavily interdependent such that it didn't make sense to split them up across the cross-platform topic branches. So here they are (for the second release in a row) in a branch on their own." * tag 'mvebu' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (88 commits) arm: l2x0: add aurora related properties to OF binding arm: mvebu: add Aurora L2 Cache Controller to the DT arm: mvebu: add L2 cache support dma: mv_xor: fix error handling path dma: mv_xor: fix error checking of irq_of_parse_and_map() dma: mv_xor: use request_irq() instead of devm_request_irq() dma: mv_xor: clear the window override control registers arm: mvebu: fix address decoding armada_cfg_base() function ARM: mvebu: update defconfig with I2C and RTC support ARM: mvebu: Add SATA support for OpenBlocks AX3-4 ARM: mvebu: Add support for the RTC in OpenBlocks AX3-4 ARM: mvebu: Add support for I2C on OpenBlocks AX3-4 ARM: mvebu: Add support for I2C controllers in Armada 370/XP arm: mvebu: Add hardware I/O Coherency support arm: plat-orion: Add coherency attribute when setup mbus target arm: dma mapping: Export a dma ops function arm_dma_set_mask arm: mvebu: Add SMP support for Armada XP arm: mm: Add support for PJ4B cpu and init routines arm: mvebu: Add IPI support via doorbells arm: mvebu: Add initial support for power managmement service unit ...
234 lines
4.8 KiB
Plaintext
234 lines
4.8 KiB
Plaintext
/include/ "skeleton.dtsi"
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/ {
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compatible = "marvell,dove";
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model = "Marvell Armada 88AP510 SoC";
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aliases {
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gpio0 = &gpio0;
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gpio1 = &gpio1;
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gpio2 = &gpio2;
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};
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soc@f1000000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&intc>;
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ranges = <0xc8000000 0xc8000000 0x0100000 /* CESA SRAM 1M */
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0xe0000000 0xe0000000 0x8000000 /* PCIe0 Mem 128M */
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0xe8000000 0xe8000000 0x8000000 /* PCIe1 Mem 128M */
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0xf0000000 0xf0000000 0x0100000 /* ScratchPad 1M */
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0x00000000 0xf1000000 0x1000000 /* SB/NB regs 16M */
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0xf2000000 0xf2000000 0x0100000 /* PCIe0 I/O 1M */
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0xf2100000 0xf2100000 0x0100000 /* PCIe0 I/O 1M */
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0xf8000000 0xf8000000 0x8000000>; /* BootROM 128M */
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l2: l2-cache {
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compatible = "marvell,tauros2-cache";
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marvell,tauros2-cache-features = <0>;
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};
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intc: interrupt-controller {
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compatible = "marvell,orion-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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reg = <0x20204 0x04>, <0x20214 0x04>;
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};
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core_clk: core-clocks@d0214 {
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compatible = "marvell,dove-core-clock";
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reg = <0xd0214 0x4>;
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#clock-cells = <1>;
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};
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gate_clk: clock-gating-control@d0038 {
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compatible = "marvell,dove-gating-clock";
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reg = <0xd0038 0x4>;
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clocks = <&core_clk 0>;
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#clock-cells = <1>;
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};
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uart0: serial@12000 {
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compatible = "ns16550a";
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reg = <0x12000 0x100>;
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reg-shift = <2>;
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interrupts = <7>;
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clock-frequency = <166666667>;
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status = "disabled";
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};
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uart1: serial@12100 {
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compatible = "ns16550a";
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reg = <0x12100 0x100>;
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reg-shift = <2>;
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interrupts = <8>;
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clock-frequency = <166666667>;
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status = "disabled";
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};
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uart2: serial@12200 {
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compatible = "ns16550a";
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reg = <0x12000 0x100>;
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reg-shift = <2>;
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interrupts = <9>;
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clock-frequency = <166666667>;
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status = "disabled";
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};
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uart3: serial@12300 {
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compatible = "ns16550a";
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reg = <0x12100 0x100>;
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reg-shift = <2>;
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interrupts = <10>;
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clock-frequency = <166666667>;
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status = "disabled";
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};
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gpio0: gpio@d0400 {
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compatible = "marvell,orion-gpio";
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#gpio-cells = <2>;
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gpio-controller;
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reg = <0xd0400 0x20>;
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ngpios = <32>;
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interrupt-controller;
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interrupts = <12>, <13>, <14>, <60>;
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};
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gpio1: gpio@d0420 {
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compatible = "marvell,orion-gpio";
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#gpio-cells = <2>;
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gpio-controller;
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reg = <0xd0420 0x20>;
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ngpios = <32>;
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interrupt-controller;
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interrupts = <61>;
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};
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gpio2: gpio@e8400 {
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compatible = "marvell,orion-gpio";
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#gpio-cells = <2>;
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gpio-controller;
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reg = <0xe8400 0x0c>;
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ngpios = <8>;
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};
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pinctrl: pinctrl@d0200 {
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compatible = "marvell,dove-pinctrl";
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reg = <0xd0200 0x10>;
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};
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spi0: spi@10600 {
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compatible = "marvell,orion-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <0>;
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interrupts = <6>;
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reg = <0x10600 0x28>;
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clocks = <&core_clk 0>;
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status = "disabled";
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};
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spi1: spi@14600 {
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compatible = "marvell,orion-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <1>;
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interrupts = <5>;
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reg = <0x14600 0x28>;
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clocks = <&core_clk 0>;
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status = "disabled";
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};
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i2c0: i2c@11000 {
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compatible = "marvell,mv64xxx-i2c";
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reg = <0x11000 0x20>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <11>;
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clock-frequency = <400000>;
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timeout-ms = <1000>;
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clocks = <&core_clk 0>;
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status = "disabled";
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};
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sdio0: sdio@92000 {
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compatible = "marvell,dove-sdhci";
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reg = <0x92000 0x100>;
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interrupts = <35>, <37>;
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clocks = <&gate_clk 8>;
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status = "disabled";
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};
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sdio1: sdio@90000 {
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compatible = "marvell,dove-sdhci";
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reg = <0x90000 0x100>;
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interrupts = <36>, <38>;
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clocks = <&gate_clk 9>;
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status = "disabled";
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};
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sata0: sata@a0000 {
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compatible = "marvell,orion-sata";
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reg = <0xa0000 0x2400>;
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interrupts = <62>;
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clocks = <&gate_clk 3>;
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nr-ports = <1>;
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status = "disabled";
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};
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crypto: crypto@30000 {
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compatible = "marvell,orion-crypto";
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reg = <0x30000 0x10000>,
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<0xc8000000 0x800>;
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reg-names = "regs", "sram";
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interrupts = <31>;
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clocks = <&gate_clk 15>;
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status = "okay";
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};
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xor0: dma-engine@60800 {
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compatible = "marvell,orion-xor";
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reg = <0x60800 0x100
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0x60a00 0x100>;
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clocks = <&gate_clk 23>;
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status = "okay";
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channel0 {
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interrupts = <39>;
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dmacap,memcpy;
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dmacap,xor;
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};
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channel1 {
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interrupts = <40>;
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dmacap,memset;
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dmacap,memcpy;
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dmacap,xor;
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};
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};
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xor1: dma-engine@60900 {
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compatible = "marvell,orion-xor";
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reg = <0x60900 0x100
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0x60b00 0x100>;
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clocks = <&gate_clk 24>;
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status = "okay";
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channel0 {
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interrupts = <42>;
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dmacap,memcpy;
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dmacap,xor;
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};
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channel1 {
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interrupts = <43>;
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dmacap,memset;
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dmacap,memcpy;
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dmacap,xor;
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};
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};
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};
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};
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