forked from Minki/linux
02b0cc52c0
The memory controller found on Tegra186 is different in some respects to its predecessors. Most notably it no longer implements an SMMU, but does assign ARM SMMU stream IDs for each memory client instead. Provide a driver that programs these registers so that memory clients can translate addresses via the ARM SMMU. Signed-off-by: Thierry Reding <treding@nvidia.com>
601 lines
10 KiB
C
601 lines
10 KiB
C
/*
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* Copyright (C) 2017 NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <dt-bindings/memory/tegra186-mc.h>
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struct tegra_mc {
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struct device *dev;
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void __iomem *regs;
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};
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struct tegra_mc_client {
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const char *name;
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unsigned int sid;
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struct {
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unsigned int override;
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unsigned int security;
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} regs;
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};
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static const struct tegra_mc_client tegra186_mc_clients[] = {
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{
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.name = "ptcr",
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.sid = TEGRA186_SID_PASSTHROUGH,
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.regs = {
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.override = 0x000,
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.security = 0x004,
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},
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}, {
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.name = "afir",
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.sid = TEGRA186_SID_AFI,
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.regs = {
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.override = 0x070,
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.security = 0x074,
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},
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}, {
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.name = "hdar",
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.sid = TEGRA186_SID_HDA,
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.regs = {
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.override = 0x0a8,
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.security = 0x0ac,
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},
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}, {
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.name = "host1xdmar",
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.sid = TEGRA186_SID_HOST1X,
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.regs = {
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.override = 0x0b0,
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.security = 0x0b4,
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},
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}, {
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.name = "nvencsrd",
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.sid = TEGRA186_SID_NVENC,
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.regs = {
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.override = 0x0e0,
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.security = 0x0e4,
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},
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}, {
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.name = "satar",
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.sid = TEGRA186_SID_SATA,
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.regs = {
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.override = 0x0f8,
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.security = 0x0fc,
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},
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}, {
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.name = "mpcorer",
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.sid = TEGRA186_SID_PASSTHROUGH,
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.regs = {
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.override = 0x138,
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.security = 0x13c,
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},
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}, {
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.name = "nvencswr",
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.sid = TEGRA186_SID_NVENC,
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.regs = {
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.override = 0x158,
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.security = 0x15c,
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},
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}, {
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.name = "afiw",
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.sid = TEGRA186_SID_AFI,
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.regs = {
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.override = 0x188,
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.security = 0x18c,
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},
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}, {
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.name = "hdaw",
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.sid = TEGRA186_SID_HDA,
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.regs = {
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.override = 0x1a8,
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.security = 0x1ac,
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},
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}, {
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.name = "mpcorew",
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.sid = TEGRA186_SID_PASSTHROUGH,
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.regs = {
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.override = 0x1c8,
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.security = 0x1cc,
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},
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}, {
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.name = "sataw",
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.sid = TEGRA186_SID_SATA,
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.regs = {
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.override = 0x1e8,
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.security = 0x1ec,
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},
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}, {
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.name = "ispra",
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.sid = TEGRA186_SID_ISP,
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.regs = {
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.override = 0x220,
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.security = 0x224,
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},
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}, {
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.name = "ispwa",
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.sid = TEGRA186_SID_ISP,
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.regs = {
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.override = 0x230,
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.security = 0x234,
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},
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}, {
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.name = "ispwb",
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.sid = TEGRA186_SID_ISP,
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.regs = {
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.override = 0x238,
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.security = 0x23c,
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},
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}, {
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.name = "xusb_hostr",
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.sid = TEGRA186_SID_XUSB_HOST,
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.regs = {
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.override = 0x250,
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.security = 0x254,
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},
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}, {
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.name = "xusb_hostw",
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.sid = TEGRA186_SID_XUSB_HOST,
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.regs = {
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.override = 0x258,
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.security = 0x25c,
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},
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}, {
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.name = "xusb_devr",
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.sid = TEGRA186_SID_XUSB_DEV,
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.regs = {
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.override = 0x260,
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.security = 0x264,
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},
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}, {
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.name = "xusb_devw",
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.sid = TEGRA186_SID_XUSB_DEV,
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.regs = {
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.override = 0x268,
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.security = 0x26c,
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},
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}, {
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.name = "tsecsrd",
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.sid = TEGRA186_SID_TSEC,
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.regs = {
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.override = 0x2a0,
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.security = 0x2a4,
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},
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}, {
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.name = "tsecswr",
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.sid = TEGRA186_SID_TSEC,
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.regs = {
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.override = 0x2a8,
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.security = 0x2ac,
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},
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}, {
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.name = "gpusrd",
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.sid = TEGRA186_SID_GPU,
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.regs = {
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.override = 0x2c0,
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.security = 0x2c4,
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},
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}, {
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.name = "gpuswr",
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.sid = TEGRA186_SID_GPU,
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.regs = {
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.override = 0x2c8,
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.security = 0x2cc,
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},
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}, {
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.name = "sdmmcra",
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.sid = TEGRA186_SID_SDMMC1,
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.regs = {
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.override = 0x300,
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.security = 0x304,
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},
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}, {
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.name = "sdmmcraa",
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.sid = TEGRA186_SID_SDMMC2,
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.regs = {
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.override = 0x308,
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.security = 0x30c,
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},
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}, {
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.name = "sdmmcr",
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.sid = TEGRA186_SID_SDMMC3,
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.regs = {
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.override = 0x310,
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.security = 0x314,
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},
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}, {
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.name = "sdmmcrab",
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.sid = TEGRA186_SID_SDMMC4,
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.regs = {
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.override = 0x318,
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.security = 0x31c,
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},
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}, {
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.name = "sdmmcwa",
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.sid = TEGRA186_SID_SDMMC1,
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.regs = {
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.override = 0x320,
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.security = 0x324,
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},
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}, {
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.name = "sdmmcwaa",
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.sid = TEGRA186_SID_SDMMC2,
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.regs = {
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.override = 0x328,
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.security = 0x32c,
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},
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}, {
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.name = "sdmmcw",
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.sid = TEGRA186_SID_SDMMC3,
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.regs = {
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.override = 0x330,
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.security = 0x334,
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},
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}, {
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.name = "sdmmcwab",
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.sid = TEGRA186_SID_SDMMC4,
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.regs = {
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.override = 0x338,
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.security = 0x33c,
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},
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}, {
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.name = "vicsrd",
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.sid = TEGRA186_SID_VIC,
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.regs = {
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.override = 0x360,
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.security = 0x364,
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},
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}, {
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.name = "vicswr",
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.sid = TEGRA186_SID_VIC,
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.regs = {
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.override = 0x368,
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.security = 0x36c,
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},
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}, {
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.name = "viw",
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.sid = TEGRA186_SID_VI,
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.regs = {
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.override = 0x390,
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.security = 0x394,
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},
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}, {
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.name = "nvdecsrd",
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.sid = TEGRA186_SID_NVDEC,
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.regs = {
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.override = 0x3c0,
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.security = 0x3c4,
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},
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}, {
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.name = "nvdecswr",
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.sid = TEGRA186_SID_NVDEC,
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.regs = {
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.override = 0x3c8,
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.security = 0x3cc,
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},
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}, {
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.name = "aper",
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.sid = TEGRA186_SID_APE,
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.regs = {
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.override = 0x3d0,
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.security = 0x3d4,
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},
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}, {
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.name = "apew",
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.sid = TEGRA186_SID_APE,
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.regs = {
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.override = 0x3d8,
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.security = 0x3dc,
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},
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}, {
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.name = "nvjpgsrd",
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.sid = TEGRA186_SID_NVJPG,
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.regs = {
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.override = 0x3f0,
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.security = 0x3f4,
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},
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}, {
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.name = "nvjpgswr",
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.sid = TEGRA186_SID_NVJPG,
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.regs = {
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.override = 0x3f8,
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.security = 0x3fc,
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},
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}, {
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.name = "sesrd",
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.sid = TEGRA186_SID_SE,
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.regs = {
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.override = 0x400,
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.security = 0x404,
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},
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}, {
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.name = "seswr",
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.sid = TEGRA186_SID_SE,
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.regs = {
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.override = 0x408,
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.security = 0x40c,
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},
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}, {
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.name = "etrr",
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.sid = TEGRA186_SID_ETR,
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.regs = {
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.override = 0x420,
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.security = 0x424,
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},
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}, {
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.name = "etrw",
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.sid = TEGRA186_SID_ETR,
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.regs = {
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.override = 0x428,
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.security = 0x42c,
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},
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}, {
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.name = "tsecsrdb",
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.sid = TEGRA186_SID_TSECB,
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.regs = {
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.override = 0x430,
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.security = 0x434,
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},
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}, {
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.name = "tsecswrb",
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.sid = TEGRA186_SID_TSECB,
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.regs = {
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.override = 0x438,
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.security = 0x43c,
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},
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}, {
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.name = "gpusrd2",
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.sid = TEGRA186_SID_GPU,
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.regs = {
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.override = 0x440,
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.security = 0x444,
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},
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}, {
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.name = "gpuswr2",
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.sid = TEGRA186_SID_GPU,
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.regs = {
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.override = 0x448,
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.security = 0x44c,
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},
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}, {
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.name = "axisr",
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.sid = TEGRA186_SID_GPCDMA_0,
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.regs = {
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.override = 0x460,
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.security = 0x464,
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},
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}, {
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.name = "axisw",
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.sid = TEGRA186_SID_GPCDMA_0,
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.regs = {
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.override = 0x468,
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.security = 0x46c,
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},
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}, {
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.name = "eqosr",
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.sid = TEGRA186_SID_EQOS,
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.regs = {
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.override = 0x470,
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.security = 0x474,
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},
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}, {
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.name = "eqosw",
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.sid = TEGRA186_SID_EQOS,
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.regs = {
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.override = 0x478,
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.security = 0x47c,
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},
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}, {
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.name = "ufshcr",
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.sid = TEGRA186_SID_UFSHC,
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.regs = {
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.override = 0x480,
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.security = 0x484,
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},
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}, {
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.name = "ufshcw",
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.sid = TEGRA186_SID_UFSHC,
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.regs = {
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.override = 0x488,
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.security = 0x48c,
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},
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}, {
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.name = "nvdisplayr",
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.sid = TEGRA186_SID_NVDISPLAY,
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.regs = {
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.override = 0x490,
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.security = 0x494,
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},
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}, {
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.name = "bpmpr",
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.sid = TEGRA186_SID_BPMP,
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.regs = {
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.override = 0x498,
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.security = 0x49c,
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},
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}, {
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.name = "bpmpw",
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.sid = TEGRA186_SID_BPMP,
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.regs = {
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.override = 0x4a0,
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.security = 0x4a4,
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},
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}, {
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.name = "bpmpdmar",
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.sid = TEGRA186_SID_BPMP,
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.regs = {
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.override = 0x4a8,
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.security = 0x4ac,
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},
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}, {
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.name = "bpmpdmaw",
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.sid = TEGRA186_SID_BPMP,
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.regs = {
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.override = 0x4b0,
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.security = 0x4b4,
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},
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}, {
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.name = "aonr",
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.sid = TEGRA186_SID_AON,
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.regs = {
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.override = 0x4b8,
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.security = 0x4bc,
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},
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}, {
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.name = "aonw",
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.sid = TEGRA186_SID_AON,
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.regs = {
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.override = 0x4c0,
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.security = 0x4c4,
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},
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}, {
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.name = "aondmar",
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.sid = TEGRA186_SID_AON,
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.regs = {
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.override = 0x4c8,
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.security = 0x4cc,
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},
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}, {
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.name = "aondmaw",
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.sid = TEGRA186_SID_AON,
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.regs = {
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.override = 0x4d0,
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.security = 0x4d4,
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},
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}, {
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.name = "scer",
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.sid = TEGRA186_SID_SCE,
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.regs = {
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.override = 0x4d8,
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.security = 0x4dc,
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},
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}, {
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.name = "scew",
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.sid = TEGRA186_SID_SCE,
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.regs = {
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.override = 0x4e0,
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.security = 0x4e4,
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},
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}, {
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.name = "scedmar",
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.sid = TEGRA186_SID_SCE,
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.regs = {
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.override = 0x4e8,
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.security = 0x4ec,
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},
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}, {
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.name = "scedmaw",
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.sid = TEGRA186_SID_SCE,
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.regs = {
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.override = 0x4f0,
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.security = 0x4f4,
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},
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}, {
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.name = "apedmar",
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.sid = TEGRA186_SID_APE,
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.regs = {
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.override = 0x4f8,
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.security = 0x4fc,
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},
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}, {
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.name = "apedmaw",
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.sid = TEGRA186_SID_APE,
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.regs = {
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.override = 0x500,
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.security = 0x504,
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},
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}, {
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.name = "nvdisplayr1",
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.sid = TEGRA186_SID_NVDISPLAY,
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.regs = {
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.override = 0x508,
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.security = 0x50c,
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},
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}, {
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.name = "vicsrd1",
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.sid = TEGRA186_SID_VIC,
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.regs = {
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.override = 0x510,
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.security = 0x514,
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},
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}, {
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.name = "nvdecsrd1",
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.sid = TEGRA186_SID_NVDEC,
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.regs = {
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.override = 0x518,
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.security = 0x51c,
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},
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},
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};
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|
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static int tegra186_mc_probe(struct platform_device *pdev)
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{
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struct resource *res;
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struct tegra_mc *mc;
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unsigned int i;
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int err = 0;
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mc = devm_kzalloc(&pdev->dev, sizeof(*mc), GFP_KERNEL);
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if (!mc)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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mc->regs = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(mc->regs))
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return PTR_ERR(mc->regs);
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mc->dev = &pdev->dev;
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for (i = 0; i < ARRAY_SIZE(tegra186_mc_clients); i++) {
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const struct tegra_mc_client *client = &tegra186_mc_clients[i];
|
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u32 override, security;
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override = readl(mc->regs + client->regs.override);
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security = readl(mc->regs + client->regs.security);
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|
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dev_dbg(&pdev->dev, "client %s: override: %x security: %x\n",
|
|
client->name, override, security);
|
|
|
|
dev_dbg(&pdev->dev, "setting SID %u for %s\n", client->sid,
|
|
client->name);
|
|
writel(client->sid, mc->regs + client->regs.override);
|
|
|
|
override = readl(mc->regs + client->regs.override);
|
|
security = readl(mc->regs + client->regs.security);
|
|
|
|
dev_dbg(&pdev->dev, "client %s: override: %x security: %x\n",
|
|
client->name, override, security);
|
|
}
|
|
|
|
platform_set_drvdata(pdev, mc);
|
|
|
|
return err;
|
|
}
|
|
|
|
static const struct of_device_id tegra186_mc_of_match[] = {
|
|
{ .compatible = "nvidia,tegra186-mc", },
|
|
{ /* sentinel */ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, tegra186_mc_of_match);
|
|
|
|
static struct platform_driver tegra186_mc_driver = {
|
|
.driver = {
|
|
.name = "tegra186-mc",
|
|
.of_match_table = tegra186_mc_of_match,
|
|
.suppress_bind_attrs = true,
|
|
},
|
|
.prevent_deferred_probe = true,
|
|
.probe = tegra186_mc_probe,
|
|
};
|
|
module_platform_driver(tegra186_mc_driver);
|
|
|
|
MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
|
|
MODULE_DESCRIPTION("NVIDIA Tegra186 Memory Controller driver");
|
|
MODULE_LICENSE("GPL v2");
|