97fb5e8d9b
Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 and only version 2 as published by the free software foundation this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 294 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190529141900.825281744@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
123 lines
4.4 KiB
C
123 lines
4.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2012-2016, The Linux Foundation. All rights reserved.
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* Copyright (C) 2017 Linaro Ltd.
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*/
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#ifndef __VENUS_HFI_VENUS_IO_H__
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#define __VENUS_HFI_VENUS_IO_H__
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#define VBIF_BASE 0x80000
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#define VBIF_AXI_HALT_CTRL0 (VBIF_BASE + 0x208)
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#define VBIF_AXI_HALT_CTRL1 (VBIF_BASE + 0x20c)
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#define VBIF_AXI_HALT_CTRL0_HALT_REQ BIT(0)
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#define VBIF_AXI_HALT_CTRL1_HALT_ACK BIT(0)
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#define VBIF_AXI_HALT_ACK_TIMEOUT_US 500000
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#define CPU_BASE 0xc0000
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#define CPU_CS_BASE (CPU_BASE + 0x12000)
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#define CPU_IC_BASE (CPU_BASE + 0x1f000)
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#define CPU_CS_A2HSOFTINTCLR (CPU_CS_BASE + 0x1c)
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#define VIDC_CTRL_INIT (CPU_CS_BASE + 0x48)
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#define VIDC_CTRL_INIT_RESERVED_BITS31_1_MASK 0xfffffffe
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#define VIDC_CTRL_INIT_RESERVED_BITS31_1_SHIFT 1
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#define VIDC_CTRL_INIT_CTRL_MASK 0x1
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#define VIDC_CTRL_INIT_CTRL_SHIFT 0
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/* HFI control status */
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#define CPU_CS_SCIACMDARG0 (CPU_CS_BASE + 0x4c)
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#define CPU_CS_SCIACMDARG0_MASK 0xff
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#define CPU_CS_SCIACMDARG0_SHIFT 0x0
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#define CPU_CS_SCIACMDARG0_ERROR_STATUS_MASK 0xfe
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#define CPU_CS_SCIACMDARG0_ERROR_STATUS_SHIFT 0x1
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#define CPU_CS_SCIACMDARG0_INIT_STATUS_MASK 0x1
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#define CPU_CS_SCIACMDARG0_INIT_STATUS_SHIFT 0x0
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#define CPU_CS_SCIACMDARG0_PC_READY BIT(8)
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#define CPU_CS_SCIACMDARG0_INIT_IDLE_MSG_MASK BIT(30)
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/* HFI queue table info */
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#define CPU_CS_SCIACMDARG1 (CPU_CS_BASE + 0x50)
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/* HFI queue table address */
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#define CPU_CS_SCIACMDARG2 (CPU_CS_BASE + 0x54)
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/* Venus cpu */
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#define CPU_CS_SCIACMDARG3 (CPU_CS_BASE + 0x58)
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#define SFR_ADDR (CPU_CS_BASE + 0x5c)
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#define MMAP_ADDR (CPU_CS_BASE + 0x60)
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#define UC_REGION_ADDR (CPU_CS_BASE + 0x64)
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#define UC_REGION_SIZE (CPU_CS_BASE + 0x68)
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#define CPU_IC_SOFTINT (CPU_IC_BASE + 0x18)
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#define CPU_IC_SOFTINT_H2A_MASK 0x8000
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#define CPU_IC_SOFTINT_H2A_SHIFT 0xf
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/* Venus wrapper */
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#define WRAPPER_BASE 0x000e0000
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#define WRAPPER_HW_VERSION (WRAPPER_BASE + 0x00)
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#define WRAPPER_HW_VERSION_MAJOR_VERSION_MASK 0x78000000
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#define WRAPPER_HW_VERSION_MAJOR_VERSION_SHIFT 28
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#define WRAPPER_HW_VERSION_MINOR_VERSION_MASK 0xfff0000
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#define WRAPPER_HW_VERSION_MINOR_VERSION_SHIFT 16
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#define WRAPPER_HW_VERSION_STEP_VERSION_MASK 0xffff
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#define WRAPPER_CLOCK_CONFIG (WRAPPER_BASE + 0x04)
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#define WRAPPER_INTR_STATUS (WRAPPER_BASE + 0x0c)
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#define WRAPPER_INTR_STATUS_A2HWD_MASK 0x10
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#define WRAPPER_INTR_STATUS_A2HWD_SHIFT 0x4
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#define WRAPPER_INTR_STATUS_A2H_MASK 0x4
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#define WRAPPER_INTR_STATUS_A2H_SHIFT 0x2
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#define WRAPPER_INTR_MASK (WRAPPER_BASE + 0x10)
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#define WRAPPER_INTR_MASK_A2HWD_BASK 0x10
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#define WRAPPER_INTR_MASK_A2HWD_SHIFT 0x4
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#define WRAPPER_INTR_MASK_A2HVCODEC_MASK 0x8
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#define WRAPPER_INTR_MASK_A2HVCODEC_SHIFT 0x3
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#define WRAPPER_INTR_MASK_A2HCPU_MASK 0x4
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#define WRAPPER_INTR_MASK_A2HCPU_SHIFT 0x2
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#define WRAPPER_INTR_CLEAR (WRAPPER_BASE + 0x14)
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#define WRAPPER_INTR_CLEAR_A2HWD_MASK 0x10
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#define WRAPPER_INTR_CLEAR_A2HWD_SHIFT 0x4
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#define WRAPPER_INTR_CLEAR_A2H_MASK 0x4
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#define WRAPPER_INTR_CLEAR_A2H_SHIFT 0x2
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#define WRAPPER_POWER_STATUS (WRAPPER_BASE + 0x44)
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#define WRAPPER_VDEC_VCODEC_POWER_CONTROL (WRAPPER_BASE + 0x48)
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#define WRAPPER_VENC_VCODEC_POWER_CONTROL (WRAPPER_BASE + 0x4c)
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#define WRAPPER_VDEC_VENC_AHB_BRIDGE_SYNC_RESET (WRAPPER_BASE + 0x64)
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#define WRAPPER_CPU_CLOCK_CONFIG (WRAPPER_BASE + 0x2000)
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#define WRAPPER_CPU_AXI_HALT (WRAPPER_BASE + 0x2008)
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#define WRAPPER_CPU_AXI_HALT_HALT BIT(16)
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#define WRAPPER_CPU_AXI_HALT_STATUS (WRAPPER_BASE + 0x200c)
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#define WRAPPER_CPU_AXI_HALT_STATUS_IDLE BIT(24)
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#define WRAPPER_CPU_CGC_DIS (WRAPPER_BASE + 0x2010)
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#define WRAPPER_CPU_STATUS (WRAPPER_BASE + 0x2014)
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#define WRAPPER_CPU_STATUS_WFI BIT(0)
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#define WRAPPER_SW_RESET (WRAPPER_BASE + 0x3000)
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#define WRAPPER_CPA_START_ADDR (WRAPPER_BASE + 0x1020)
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#define WRAPPER_CPA_END_ADDR (WRAPPER_BASE + 0x1024)
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#define WRAPPER_FW_START_ADDR (WRAPPER_BASE + 0x1028)
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#define WRAPPER_FW_END_ADDR (WRAPPER_BASE + 0x102C)
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#define WRAPPER_NONPIX_START_ADDR (WRAPPER_BASE + 0x1030)
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#define WRAPPER_NONPIX_END_ADDR (WRAPPER_BASE + 0x1034)
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#define WRAPPER_A9SS_SW_RESET (WRAPPER_BASE + 0x3000)
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#define WRAPPER_A9SS_SW_RESET_BIT BIT(4)
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/* Venus 4xx */
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#define WRAPPER_VCODEC0_MMCC_POWER_STATUS (WRAPPER_BASE + 0x90)
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#define WRAPPER_VCODEC0_MMCC_POWER_CONTROL (WRAPPER_BASE + 0x94)
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#define WRAPPER_VCODEC1_MMCC_POWER_STATUS (WRAPPER_BASE + 0x110)
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#define WRAPPER_VCODEC1_MMCC_POWER_CONTROL (WRAPPER_BASE + 0x114)
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#endif
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