031c8cd8bd
i.MX6SLL also has a pxp, so mention it among others in the bindings doc. Signed-off-by: Andreas Kemnade <andreas@kemnade.info> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
27 lines
895 B
Plaintext
27 lines
895 B
Plaintext
Freescale Pixel Pipeline
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========================
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The Pixel Pipeline (PXP) is a memory-to-memory graphics processing engine
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that supports scaling, colorspace conversion, alpha blending, rotation, and
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pixel conversion via lookup table. Different versions are present on various
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i.MX SoCs from i.MX23 to i.MX7.
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Required properties:
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- compatible: should be "fsl,<soc>-pxp", where SoC can be one of imx23, imx28,
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imx6dl, imx6sl, imx6sll, imx6ul, imx6sx, imx6ull, or imx7d.
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- reg: the register base and size for the device registers
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- interrupts: the PXP interrupt, two interrupts for imx6ull and imx7d.
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- clock-names: should be "axi"
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- clocks: the PXP AXI clock
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Example:
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pxp@21cc000 {
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compatible = "fsl,imx6ull-pxp";
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reg = <0x021cc000 0x4000>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "axi";
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clocks = <&clks IMX6UL_CLK_PXP>;
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};
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