forked from Minki/linux
5138d5c562
The gpio4 and gpio5 are in 0xf7fc0000 apb which is located in the SM domain.
This patch moves gpio4 and gpio5 to the correct location. This patch also
renames them as the following to match the names we internally used in
marvell:
gpio4 -> sm_gpio1
gpio5 -> sm_gpio0
porte -> portf
portf -> porte
This also matches what we did for BG2 and BG2CD's SM GPIO.
Cc: stable@vger.kernel.org # 3.16+
Fixes: cedf57fc4f ("ARM: dts: berlin: add the BG2Q GPIO nodes")
Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
556 lines
12 KiB
Plaintext
556 lines
12 KiB
Plaintext
/*
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* Copyright (C) 2014 Antoine Ténart <antoine.tenart@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <dt-bindings/clock/berlin2q.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include "skeleton.dtsi"
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/ {
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model = "Marvell Armada 1500 pro (BG2-Q) SoC";
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compatible = "marvell,berlin2q", "marvell,berlin";
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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enable-method = "marvell,berlin-smp";
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cpu@0 {
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compatible = "arm,cortex-a9";
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device_type = "cpu";
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next-level-cache = <&l2>;
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reg = <0>;
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};
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cpu@1 {
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compatible = "arm,cortex-a9";
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device_type = "cpu";
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next-level-cache = <&l2>;
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reg = <1>;
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};
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cpu@2 {
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compatible = "arm,cortex-a9";
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device_type = "cpu";
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next-level-cache = <&l2>;
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reg = <2>;
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};
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cpu@3 {
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compatible = "arm,cortex-a9";
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device_type = "cpu";
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next-level-cache = <&l2>;
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reg = <3>;
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};
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};
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refclk: oscillator {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <25000000>;
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0xf7000000 0x1000000>;
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interrupt-parent = <&gic>;
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sdhci0: sdhci@ab0000 {
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compatible = "mrvl,pxav3-mmc";
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reg = <0xab0000 0x200>;
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clocks = <&chip CLKID_SDIO1XIN>;
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interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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sdhci1: sdhci@ab0800 {
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compatible = "mrvl,pxav3-mmc";
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reg = <0xab0800 0x200>;
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clocks = <&chip CLKID_SDIO1XIN>;
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interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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sdhci2: sdhci@ab1000 {
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compatible = "mrvl,pxav3-mmc";
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reg = <0xab1000 0x200>;
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interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&chip CLKID_NFC_ECC>, <&chip CLKID_NFC>;
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clock-names = "io", "core";
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status = "disabled";
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};
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l2: l2-cache-controller@ac0000 {
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compatible = "arm,pl310-cache";
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reg = <0xac0000 0x1000>;
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cache-level = <2>;
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arm,data-latency = <2 2 2>;
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arm,tag-latency = <2 2 2>;
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};
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scu: snoop-control-unit@ad0000 {
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compatible = "arm,cortex-a9-scu";
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reg = <0xad0000 0x58>;
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};
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local-timer@ad0600 {
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compatible = "arm,cortex-a9-twd-timer";
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reg = <0xad0600 0x20>;
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clocks = <&chip CLKID_TWD>;
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
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};
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gic: interrupt-controller@ad1000 {
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compatible = "arm,cortex-a9-gic";
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reg = <0xad1000 0x1000>, <0xad0100 0x100>;
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interrupt-controller;
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#interrupt-cells = <3>;
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};
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usb_phy2: phy@a2f400 {
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compatible = "marvell,berlin2-usb-phy";
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reg = <0xa2f400 0x128>;
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#phy-cells = <0>;
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resets = <&chip 0x104 14>;
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status = "disabled";
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};
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usb2: usb@a30000 {
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compatible = "chipidea,usb2";
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reg = <0xa30000 0x10000>;
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interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&chip CLKID_USB2>;
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phys = <&usb_phy2>;
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phy-names = "usb-phy";
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status = "disabled";
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};
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usb_phy0: phy@b74000 {
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compatible = "marvell,berlin2-usb-phy";
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reg = <0xb74000 0x128>;
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#phy-cells = <0>;
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resets = <&chip 0x104 12>;
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status = "disabled";
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};
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usb_phy1: phy@b78000 {
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compatible = "marvell,berlin2-usb-phy";
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reg = <0xb78000 0x128>;
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#phy-cells = <0>;
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resets = <&chip 0x104 13>;
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status = "disabled";
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};
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eth0: ethernet@b90000 {
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compatible = "marvell,pxa168-eth";
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reg = <0xb90000 0x10000>;
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clocks = <&chip CLKID_GETH0>;
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interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
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/* set by bootloader */
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local-mac-address = [00 00 00 00 00 00];
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#address-cells = <1>;
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#size-cells = <0>;
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phy-connection-type = "mii";
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phy-handle = <ðphy0>;
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status = "disabled";
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ethphy0: ethernet-phy@0 {
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reg = <0>;
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};
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};
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cpu-ctrl@dd0000 {
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compatible = "marvell,berlin-cpu-ctrl";
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reg = <0xdd0000 0x10000>;
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};
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apb@e80000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0xe80000 0x10000>;
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interrupt-parent = <&aic>;
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gpio0: gpio@0400 {
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compatible = "snps,dw-apb-gpio";
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reg = <0x0400 0x400>;
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#address-cells = <1>;
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#size-cells = <0>;
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porta: gpio-port@0 {
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compatible = "snps,dw-apb-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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snps,nr-gpios = <32>;
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reg = <0>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <0>;
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};
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};
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gpio1: gpio@0800 {
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compatible = "snps,dw-apb-gpio";
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reg = <0x0800 0x400>;
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#address-cells = <1>;
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#size-cells = <0>;
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portb: gpio-port@1 {
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compatible = "snps,dw-apb-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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snps,nr-gpios = <32>;
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reg = <0>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <1>;
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};
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};
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gpio2: gpio@0c00 {
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compatible = "snps,dw-apb-gpio";
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reg = <0x0c00 0x400>;
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#address-cells = <1>;
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#size-cells = <0>;
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portc: gpio-port@2 {
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compatible = "snps,dw-apb-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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snps,nr-gpios = <32>;
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reg = <0>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <2>;
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};
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};
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gpio3: gpio@1000 {
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compatible = "snps,dw-apb-gpio";
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reg = <0x1000 0x400>;
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#address-cells = <1>;
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#size-cells = <0>;
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portd: gpio-port@3 {
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compatible = "snps,dw-apb-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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snps,nr-gpios = <32>;
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reg = <0>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <3>;
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};
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};
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i2c0: i2c@1400 {
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compatible = "snps,designware-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x1400 0x100>;
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interrupt-parent = <&aic>;
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interrupts = <4>;
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clocks = <&chip CLKID_CFG>;
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pinctrl-0 = <&twsi0_pmux>;
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pinctrl-names = "default";
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status = "disabled";
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};
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i2c1: i2c@1800 {
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compatible = "snps,designware-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x1800 0x100>;
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interrupt-parent = <&aic>;
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interrupts = <5>;
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clocks = <&chip CLKID_CFG>;
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pinctrl-0 = <&twsi1_pmux>;
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pinctrl-names = "default";
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status = "disabled";
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};
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timer0: timer@2c00 {
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compatible = "snps,dw-apb-timer";
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reg = <0x2c00 0x14>;
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clocks = <&chip CLKID_CFG>;
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clock-names = "timer";
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interrupts = <8>;
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};
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timer1: timer@2c14 {
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compatible = "snps,dw-apb-timer";
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reg = <0x2c14 0x14>;
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clocks = <&chip CLKID_CFG>;
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clock-names = "timer";
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};
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timer2: timer@2c28 {
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compatible = "snps,dw-apb-timer";
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reg = <0x2c28 0x14>;
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clocks = <&chip CLKID_CFG>;
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clock-names = "timer";
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status = "disabled";
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};
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timer3: timer@2c3c {
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compatible = "snps,dw-apb-timer";
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reg = <0x2c3c 0x14>;
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clocks = <&chip CLKID_CFG>;
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clock-names = "timer";
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status = "disabled";
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};
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timer4: timer@2c50 {
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compatible = "snps,dw-apb-timer";
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reg = <0x2c50 0x14>;
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clocks = <&chip CLKID_CFG>;
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clock-names = "timer";
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status = "disabled";
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};
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timer5: timer@2c64 {
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compatible = "snps,dw-apb-timer";
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reg = <0x2c64 0x14>;
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clocks = <&chip CLKID_CFG>;
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clock-names = "timer";
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status = "disabled";
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};
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timer6: timer@2c78 {
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compatible = "snps,dw-apb-timer";
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reg = <0x2c78 0x14>;
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clocks = <&chip CLKID_CFG>;
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clock-names = "timer";
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status = "disabled";
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};
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timer7: timer@2c8c {
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compatible = "snps,dw-apb-timer";
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reg = <0x2c8c 0x14>;
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clocks = <&chip CLKID_CFG>;
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clock-names = "timer";
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status = "disabled";
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};
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aic: interrupt-controller@3800 {
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compatible = "snps,dw-apb-ictl";
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reg = <0x3800 0x30>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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chip: chip-control@ea0000 {
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compatible = "marvell,berlin2q-chip-ctrl";
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#clock-cells = <1>;
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#reset-cells = <2>;
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reg = <0xea0000 0x400>, <0xdd0170 0x10>;
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clocks = <&refclk>;
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clock-names = "refclk";
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twsi0_pmux: twsi0-pmux {
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groups = "G6";
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function = "twsi0";
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};
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twsi1_pmux: twsi1-pmux {
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groups = "G7";
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function = "twsi1";
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};
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};
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ahci: sata@e90000 {
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compatible = "marvell,berlin2q-ahci", "generic-ahci";
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reg = <0xe90000 0x1000>;
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interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&chip CLKID_SATA>;
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#address-cells = <1>;
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#size-cells = <0>;
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sata0: sata-port@0 {
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reg = <0>;
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phys = <&sata_phy 0>;
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status = "disabled";
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};
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sata1: sata-port@1 {
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reg = <1>;
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phys = <&sata_phy 1>;
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status = "disabled";
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};
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};
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sata_phy: phy@e900a0 {
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compatible = "marvell,berlin2q-sata-phy";
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reg = <0xe900a0 0x200>;
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clocks = <&chip CLKID_SATA>;
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#address-cells = <1>;
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#size-cells = <0>;
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#phy-cells = <1>;
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status = "disabled";
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sata-phy@0 {
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reg = <0>;
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};
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sata-phy@1 {
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reg = <1>;
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};
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};
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usb0: usb@ed0000 {
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compatible = "chipidea,usb2";
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reg = <0xed0000 0x10000>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&chip CLKID_USB0>;
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phys = <&usb_phy0>;
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phy-names = "usb-phy";
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status = "disabled";
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};
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usb1: usb@ee0000 {
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compatible = "chipidea,usb2";
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reg = <0xee0000 0x10000>;
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interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&chip CLKID_USB1>;
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phys = <&usb_phy1>;
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phy-names = "usb-phy";
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status = "disabled";
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};
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apb@fc0000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0xfc0000 0x10000>;
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interrupt-parent = <&sic>;
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sm_gpio1: gpio@5000 {
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compatible = "snps,dw-apb-gpio";
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reg = <0x5000 0x400>;
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#address-cells = <1>;
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#size-cells = <0>;
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portf: gpio-port@5 {
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compatible = "snps,dw-apb-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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snps,nr-gpios = <32>;
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reg = <0>;
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};
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};
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i2c2: i2c@7000 {
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compatible = "snps,designware-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x7000 0x100>;
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interrupt-parent = <&sic>;
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interrupts = <6>;
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clocks = <&refclk>;
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pinctrl-0 = <&twsi2_pmux>;
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pinctrl-names = "default";
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status = "disabled";
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};
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i2c3: i2c@8000 {
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compatible = "snps,designware-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x8000 0x100>;
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interrupt-parent = <&sic>;
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interrupts = <7>;
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clocks = <&refclk>;
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pinctrl-0 = <&twsi3_pmux>;
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pinctrl-names = "default";
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status = "disabled";
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};
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uart0: uart@9000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x9000 0x100>;
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interrupt-parent = <&sic>;
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interrupts = <8>;
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clocks = <&refclk>;
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reg-shift = <2>;
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pinctrl-0 = <&uart0_pmux>;
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pinctrl-names = "default";
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status = "disabled";
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};
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uart1: uart@a000 {
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compatible = "snps,dw-apb-uart";
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reg = <0xa000 0x100>;
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interrupt-parent = <&sic>;
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interrupts = <9>;
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clocks = <&refclk>;
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reg-shift = <2>;
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pinctrl-0 = <&uart1_pmux>;
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pinctrl-names = "default";
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status = "disabled";
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};
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sm_gpio0: gpio@c000 {
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compatible = "snps,dw-apb-gpio";
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reg = <0xc000 0x400>;
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#address-cells = <1>;
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#size-cells = <0>;
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porte: gpio-port@4 {
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compatible = "snps,dw-apb-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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snps,nr-gpios = <32>;
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reg = <0>;
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};
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};
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sysctrl: pin-controller@d000 {
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compatible = "marvell,berlin2q-system-ctrl";
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reg = <0xd000 0x100>;
|
|
|
|
uart0_pmux: uart0-pmux {
|
|
groups = "GSM12";
|
|
function = "uart0";
|
|
};
|
|
|
|
uart1_pmux: uart1-pmux {
|
|
groups = "GSM14";
|
|
function = "uart1";
|
|
};
|
|
|
|
twsi2_pmux: twsi2-pmux {
|
|
groups = "GSM13";
|
|
function = "twsi2";
|
|
};
|
|
|
|
twsi3_pmux: twsi3-pmux {
|
|
groups = "GSM14";
|
|
function = "twsi3";
|
|
};
|
|
};
|
|
|
|
sic: interrupt-controller@e000 {
|
|
compatible = "snps,dw-apb-ictl";
|
|
reg = <0xe000 0x30>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <1>;
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
};
|
|
};
|
|
};
|