forked from Minki/linux
51576d3603
This patch adds I2C1 support for STM32F429 SoC Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: M'boumba Cedric Madianga <cedric.madianga@gmail.com> Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
822 lines
19 KiB
Plaintext
822 lines
19 KiB
Plaintext
/*
|
|
* Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
|
|
*
|
|
* This file is dual-licensed: you can use it either under the terms
|
|
* of the GPL or the X11 license, at your option. Note that this dual
|
|
* licensing only applies to this file, and not this project as a
|
|
* whole.
|
|
*
|
|
* a) This file is free software; you can redistribute it and/or
|
|
* modify it under the terms of the GNU General Public License as
|
|
* published by the Free Software Foundation; either version 2 of the
|
|
* License, or (at your option) any later version.
|
|
*
|
|
* This file is distributed in the hope that it will be useful,
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
* GNU General Public License for more details.
|
|
*
|
|
* You should have received a copy of the GNU General Public
|
|
* License along with this file; if not, write to the Free
|
|
* Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
|
|
* MA 02110-1301 USA
|
|
*
|
|
* Or, alternatively,
|
|
*
|
|
* b) Permission is hereby granted, free of charge, to any person
|
|
* obtaining a copy of this software and associated documentation
|
|
* files (the "Software"), to deal in the Software without
|
|
* restriction, including without limitation the rights to use,
|
|
* copy, modify, merge, publish, distribute, sublicense, and/or
|
|
* sell copies of the Software, and to permit persons to whom the
|
|
* Software is furnished to do so, subject to the following
|
|
* conditions:
|
|
*
|
|
* The above copyright notice and this permission notice shall be
|
|
* included in all copies or substantial portions of the Software.
|
|
*
|
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
|
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
|
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
|
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
|
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
|
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
|
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
|
* OTHER DEALINGS IN THE SOFTWARE.
|
|
*/
|
|
|
|
#include "skeleton.dtsi"
|
|
#include "armv7-m.dtsi"
|
|
#include <dt-bindings/pinctrl/stm32f429-pinfunc.h>
|
|
#include <dt-bindings/clock/stm32fx-clock.h>
|
|
#include <dt-bindings/mfd/stm32f4-rcc.h>
|
|
|
|
/ {
|
|
clocks {
|
|
clk_hse: clk-hse {
|
|
#clock-cells = <0>;
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <0>;
|
|
};
|
|
|
|
clk-lse {
|
|
#clock-cells = <0>;
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <32768>;
|
|
};
|
|
|
|
clk-lsi {
|
|
#clock-cells = <0>;
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <32000>;
|
|
};
|
|
|
|
clk_i2s_ckin: i2s-ckin {
|
|
#clock-cells = <0>;
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <0>;
|
|
};
|
|
};
|
|
|
|
soc {
|
|
timer2: timer@40000000 {
|
|
compatible = "st,stm32-timer";
|
|
reg = <0x40000000 0x400>;
|
|
interrupts = <28>;
|
|
clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
|
|
status = "disabled";
|
|
};
|
|
|
|
timers2: timers@40000000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "st,stm32-timers";
|
|
reg = <0x40000000 0x400>;
|
|
clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
|
|
clock-names = "int";
|
|
status = "disabled";
|
|
|
|
pwm {
|
|
compatible = "st,stm32-pwm";
|
|
status = "disabled";
|
|
};
|
|
|
|
timer@1 {
|
|
compatible = "st,stm32-timer-trigger";
|
|
reg = <1>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
timer3: timer@40000400 {
|
|
compatible = "st,stm32-timer";
|
|
reg = <0x40000400 0x400>;
|
|
interrupts = <29>;
|
|
clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
|
|
status = "disabled";
|
|
};
|
|
|
|
timers3: timers@40000400 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "st,stm32-timers";
|
|
reg = <0x40000400 0x400>;
|
|
clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
|
|
clock-names = "int";
|
|
status = "disabled";
|
|
|
|
pwm {
|
|
compatible = "st,stm32-pwm";
|
|
status = "disabled";
|
|
};
|
|
|
|
timer@2 {
|
|
compatible = "st,stm32-timer-trigger";
|
|
reg = <2>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
timer4: timer@40000800 {
|
|
compatible = "st,stm32-timer";
|
|
reg = <0x40000800 0x400>;
|
|
interrupts = <30>;
|
|
clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
|
|
status = "disabled";
|
|
};
|
|
|
|
timers4: timers@40000800 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "st,stm32-timers";
|
|
reg = <0x40000800 0x400>;
|
|
clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
|
|
clock-names = "int";
|
|
status = "disabled";
|
|
|
|
pwm {
|
|
compatible = "st,stm32-pwm";
|
|
status = "disabled";
|
|
};
|
|
|
|
timer@3 {
|
|
compatible = "st,stm32-timer-trigger";
|
|
reg = <3>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
timer5: timer@40000c00 {
|
|
compatible = "st,stm32-timer";
|
|
reg = <0x40000c00 0x400>;
|
|
interrupts = <50>;
|
|
clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
|
|
};
|
|
|
|
timers5: timers@40000c00 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "st,stm32-timers";
|
|
reg = <0x40000C00 0x400>;
|
|
clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
|
|
clock-names = "int";
|
|
status = "disabled";
|
|
|
|
pwm {
|
|
compatible = "st,stm32-pwm";
|
|
status = "disabled";
|
|
};
|
|
|
|
timer@4 {
|
|
compatible = "st,stm32-timer-trigger";
|
|
reg = <4>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
timer6: timer@40001000 {
|
|
compatible = "st,stm32-timer";
|
|
reg = <0x40001000 0x400>;
|
|
interrupts = <54>;
|
|
clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
|
|
status = "disabled";
|
|
};
|
|
|
|
timers6: timers@40001000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "st,stm32-timers";
|
|
reg = <0x40001000 0x400>;
|
|
clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
|
|
clock-names = "int";
|
|
status = "disabled";
|
|
|
|
timer@5 {
|
|
compatible = "st,stm32-timer-trigger";
|
|
reg = <5>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
timer7: timer@40001400 {
|
|
compatible = "st,stm32-timer";
|
|
reg = <0x40001400 0x400>;
|
|
interrupts = <55>;
|
|
clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
|
|
status = "disabled";
|
|
};
|
|
|
|
timers7: timers@40001400 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "st,stm32-timers";
|
|
reg = <0x40001400 0x400>;
|
|
clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
|
|
clock-names = "int";
|
|
status = "disabled";
|
|
|
|
timer@6 {
|
|
compatible = "st,stm32-timer-trigger";
|
|
reg = <6>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
timers12: timers@40001800 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "st,stm32-timers";
|
|
reg = <0x40001800 0x400>;
|
|
clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM12)>;
|
|
clock-names = "int";
|
|
status = "disabled";
|
|
|
|
pwm {
|
|
compatible = "st,stm32-pwm";
|
|
status = "disabled";
|
|
};
|
|
|
|
timer@11 {
|
|
compatible = "st,stm32-timer-trigger";
|
|
reg = <11>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
timers13: timers@40001c00 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "st,stm32-timers";
|
|
reg = <0x40001C00 0x400>;
|
|
clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM13)>;
|
|
clock-names = "int";
|
|
status = "disabled";
|
|
|
|
pwm {
|
|
compatible = "st,stm32-pwm";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
timers14: timers@40002000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "st,stm32-timers";
|
|
reg = <0x40002000 0x400>;
|
|
clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM14)>;
|
|
clock-names = "int";
|
|
status = "disabled";
|
|
|
|
pwm {
|
|
compatible = "st,stm32-pwm";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
rtc: rtc@40002800 {
|
|
compatible = "st,stm32-rtc";
|
|
reg = <0x40002800 0x400>;
|
|
clocks = <&rcc 1 CLK_RTC>;
|
|
clock-names = "ck_rtc";
|
|
assigned-clocks = <&rcc 1 CLK_RTC>;
|
|
assigned-clock-parents = <&rcc 1 CLK_LSE>;
|
|
interrupt-parent = <&exti>;
|
|
interrupts = <17 1>;
|
|
interrupt-names = "alarm";
|
|
st,syscfg = <&pwrcfg>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usart2: serial@40004400 {
|
|
compatible = "st,stm32-usart", "st,stm32-uart";
|
|
reg = <0x40004400 0x400>;
|
|
interrupts = <38>;
|
|
clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART2)>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usart3: serial@40004800 {
|
|
compatible = "st,stm32-usart", "st,stm32-uart";
|
|
reg = <0x40004800 0x400>;
|
|
interrupts = <39>;
|
|
clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART3)>;
|
|
status = "disabled";
|
|
dmas = <&dma1 1 4 0x400 0x0>,
|
|
<&dma1 3 4 0x400 0x0>;
|
|
dma-names = "rx", "tx";
|
|
};
|
|
|
|
usart4: serial@40004c00 {
|
|
compatible = "st,stm32-uart";
|
|
reg = <0x40004c00 0x400>;
|
|
interrupts = <52>;
|
|
clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART4)>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usart5: serial@40005000 {
|
|
compatible = "st,stm32-uart";
|
|
reg = <0x40005000 0x400>;
|
|
interrupts = <53>;
|
|
clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART5)>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c1: i2c@40005400 {
|
|
compatible = "st,stm32f4-i2c";
|
|
reg = <0x40005400 0x400>;
|
|
interrupts = <31>,
|
|
<32>;
|
|
resets = <&rcc STM32F4_APB1_RESET(I2C1)>;
|
|
clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C1)>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usart7: serial@40007800 {
|
|
compatible = "st,stm32-usart", "st,stm32-uart";
|
|
reg = <0x40007800 0x400>;
|
|
interrupts = <82>;
|
|
clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART7)>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usart8: serial@40007c00 {
|
|
compatible = "st,stm32-usart", "st,stm32-uart";
|
|
reg = <0x40007c00 0x400>;
|
|
interrupts = <83>;
|
|
clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART8)>;
|
|
status = "disabled";
|
|
};
|
|
|
|
timers1: timers@40010000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "st,stm32-timers";
|
|
reg = <0x40010000 0x400>;
|
|
clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM1)>;
|
|
clock-names = "int";
|
|
status = "disabled";
|
|
|
|
pwm {
|
|
compatible = "st,stm32-pwm";
|
|
status = "disabled";
|
|
};
|
|
|
|
timer@0 {
|
|
compatible = "st,stm32-timer-trigger";
|
|
reg = <0>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
timers8: timers@40010400 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "st,stm32-timers";
|
|
reg = <0x40010400 0x400>;
|
|
clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM8)>;
|
|
clock-names = "int";
|
|
status = "disabled";
|
|
|
|
pwm {
|
|
compatible = "st,stm32-pwm";
|
|
status = "disabled";
|
|
};
|
|
|
|
timer@7 {
|
|
compatible = "st,stm32-timer-trigger";
|
|
reg = <7>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
usart1: serial@40011000 {
|
|
compatible = "st,stm32-usart", "st,stm32-uart";
|
|
reg = <0x40011000 0x400>;
|
|
interrupts = <37>;
|
|
clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART1)>;
|
|
status = "disabled";
|
|
dmas = <&dma2 2 4 0x400 0x0>,
|
|
<&dma2 7 4 0x400 0x0>;
|
|
dma-names = "rx", "tx";
|
|
};
|
|
|
|
usart6: serial@40011400 {
|
|
compatible = "st,stm32-usart", "st,stm32-uart";
|
|
reg = <0x40011400 0x400>;
|
|
interrupts = <71>;
|
|
clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART6)>;
|
|
status = "disabled";
|
|
};
|
|
|
|
adc: adc@40012000 {
|
|
compatible = "st,stm32f4-adc-core";
|
|
reg = <0x40012000 0x400>;
|
|
interrupts = <18>;
|
|
clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
|
|
clock-names = "adc";
|
|
interrupt-controller;
|
|
#interrupt-cells = <1>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
|
|
adc1: adc@0 {
|
|
compatible = "st,stm32f4-adc";
|
|
#io-channel-cells = <1>;
|
|
reg = <0x0>;
|
|
clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
|
|
interrupt-parent = <&adc>;
|
|
interrupts = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
adc2: adc@100 {
|
|
compatible = "st,stm32f4-adc";
|
|
#io-channel-cells = <1>;
|
|
reg = <0x100>;
|
|
clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC2)>;
|
|
interrupt-parent = <&adc>;
|
|
interrupts = <1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
adc3: adc@200 {
|
|
compatible = "st,stm32f4-adc";
|
|
#io-channel-cells = <1>;
|
|
reg = <0x200>;
|
|
clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC3)>;
|
|
interrupt-parent = <&adc>;
|
|
interrupts = <2>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
syscfg: system-config@40013800 {
|
|
compatible = "syscon";
|
|
reg = <0x40013800 0x400>;
|
|
};
|
|
|
|
exti: interrupt-controller@40013c00 {
|
|
compatible = "st,stm32-exti";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
reg = <0x40013C00 0x400>;
|
|
interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
|
|
};
|
|
|
|
timers9: timers@40014000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "st,stm32-timers";
|
|
reg = <0x40014000 0x400>;
|
|
clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM9)>;
|
|
clock-names = "int";
|
|
status = "disabled";
|
|
|
|
pwm {
|
|
compatible = "st,stm32-pwm";
|
|
status = "disabled";
|
|
};
|
|
|
|
timer@8 {
|
|
compatible = "st,stm32-timer-trigger";
|
|
reg = <8>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
timers10: timers@40014400 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "st,stm32-timers";
|
|
reg = <0x40014400 0x400>;
|
|
clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM10)>;
|
|
clock-names = "int";
|
|
status = "disabled";
|
|
|
|
pwm {
|
|
compatible = "st,stm32-pwm";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
timers11: timers@40014800 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "st,stm32-timers";
|
|
reg = <0x40014800 0x400>;
|
|
clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM11)>;
|
|
clock-names = "int";
|
|
status = "disabled";
|
|
|
|
pwm {
|
|
compatible = "st,stm32-pwm";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
pwrcfg: power-config@40007000 {
|
|
compatible = "syscon";
|
|
reg = <0x40007000 0x400>;
|
|
};
|
|
|
|
pin-controller {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
compatible = "st,stm32f429-pinctrl";
|
|
ranges = <0 0x40020000 0x3000>;
|
|
interrupt-parent = <&exti>;
|
|
st,syscfg = <&syscfg 0x8>;
|
|
pins-are-numbered;
|
|
|
|
gpioa: gpio@40020000 {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
reg = <0x0 0x400>;
|
|
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>;
|
|
st,bank-name = "GPIOA";
|
|
};
|
|
|
|
gpiob: gpio@40020400 {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
reg = <0x400 0x400>;
|
|
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOB)>;
|
|
st,bank-name = "GPIOB";
|
|
};
|
|
|
|
gpioc: gpio@40020800 {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
reg = <0x800 0x400>;
|
|
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOC)>;
|
|
st,bank-name = "GPIOC";
|
|
};
|
|
|
|
gpiod: gpio@40020c00 {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
reg = <0xc00 0x400>;
|
|
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOD)>;
|
|
st,bank-name = "GPIOD";
|
|
};
|
|
|
|
gpioe: gpio@40021000 {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
reg = <0x1000 0x400>;
|
|
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOE)>;
|
|
st,bank-name = "GPIOE";
|
|
};
|
|
|
|
gpiof: gpio@40021400 {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
reg = <0x1400 0x400>;
|
|
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOF)>;
|
|
st,bank-name = "GPIOF";
|
|
};
|
|
|
|
gpiog: gpio@40021800 {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
reg = <0x1800 0x400>;
|
|
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOG)>;
|
|
st,bank-name = "GPIOG";
|
|
};
|
|
|
|
gpioh: gpio@40021c00 {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
reg = <0x1c00 0x400>;
|
|
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOH)>;
|
|
st,bank-name = "GPIOH";
|
|
};
|
|
|
|
gpioi: gpio@40022000 {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
reg = <0x2000 0x400>;
|
|
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOI)>;
|
|
st,bank-name = "GPIOI";
|
|
};
|
|
|
|
gpioj: gpio@40022400 {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
reg = <0x2400 0x400>;
|
|
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOJ)>;
|
|
st,bank-name = "GPIOJ";
|
|
};
|
|
|
|
gpiok: gpio@40022800 {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
reg = <0x2800 0x400>;
|
|
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOK)>;
|
|
st,bank-name = "GPIOK";
|
|
};
|
|
|
|
usart1_pins_a: usart1@0 {
|
|
pins1 {
|
|
pinmux = <STM32F429_PA9_FUNC_USART1_TX>;
|
|
bias-disable;
|
|
drive-push-pull;
|
|
slew-rate = <0>;
|
|
};
|
|
pins2 {
|
|
pinmux = <STM32F429_PA10_FUNC_USART1_RX>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
usart3_pins_a: usart3@0 {
|
|
pins1 {
|
|
pinmux = <STM32F429_PB10_FUNC_USART3_TX>;
|
|
bias-disable;
|
|
drive-push-pull;
|
|
slew-rate = <0>;
|
|
};
|
|
pins2 {
|
|
pinmux = <STM32F429_PB11_FUNC_USART3_RX>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
usbotg_hs_pins_a: usbotg_hs@0 {
|
|
pins {
|
|
pinmux = <STM32F429_PH4_FUNC_OTG_HS_ULPI_NXT>,
|
|
<STM32F429_PI11_FUNC_OTG_HS_ULPI_DIR>,
|
|
<STM32F429_PC0_FUNC_OTG_HS_ULPI_STP>,
|
|
<STM32F429_PA5_FUNC_OTG_HS_ULPI_CK>,
|
|
<STM32F429_PA3_FUNC_OTG_HS_ULPI_D0>,
|
|
<STM32F429_PB0_FUNC_OTG_HS_ULPI_D1>,
|
|
<STM32F429_PB1_FUNC_OTG_HS_ULPI_D2>,
|
|
<STM32F429_PB10_FUNC_OTG_HS_ULPI_D3>,
|
|
<STM32F429_PB11_FUNC_OTG_HS_ULPI_D4>,
|
|
<STM32F429_PB12_FUNC_OTG_HS_ULPI_D5>,
|
|
<STM32F429_PB13_FUNC_OTG_HS_ULPI_D6>,
|
|
<STM32F429_PB5_FUNC_OTG_HS_ULPI_D7>;
|
|
bias-disable;
|
|
drive-push-pull;
|
|
slew-rate = <2>;
|
|
};
|
|
};
|
|
|
|
ethernet_mii: mii@0 {
|
|
pins {
|
|
pinmux = <STM32F429_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>,
|
|
<STM32F429_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>,
|
|
<STM32F429_PC2_FUNC_ETH_MII_TXD2>,
|
|
<STM32F429_PB8_FUNC_ETH_MII_TXD3>,
|
|
<STM32F429_PC3_FUNC_ETH_MII_TX_CLK>,
|
|
<STM32F429_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN>,
|
|
<STM32F429_PA2_FUNC_ETH_MDIO>,
|
|
<STM32F429_PC1_FUNC_ETH_MDC>,
|
|
<STM32F429_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK>,
|
|
<STM32F429_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV>,
|
|
<STM32F429_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0>,
|
|
<STM32F429_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1>,
|
|
<STM32F429_PH6_FUNC_ETH_MII_RXD2>,
|
|
<STM32F429_PH7_FUNC_ETH_MII_RXD3>;
|
|
slew-rate = <2>;
|
|
};
|
|
};
|
|
|
|
adc3_in8_pin: adc@200 {
|
|
pins {
|
|
pinmux = <STM32F429_PF10_FUNC_ANALOG>;
|
|
};
|
|
};
|
|
|
|
pwm1_pins: pwm@1 {
|
|
pins {
|
|
pinmux = <STM32F429_PA8_FUNC_TIM1_CH1>,
|
|
<STM32F429_PB13_FUNC_TIM1_CH1N>,
|
|
<STM32F429_PB12_FUNC_TIM1_BKIN>;
|
|
};
|
|
};
|
|
|
|
pwm3_pins: pwm@3 {
|
|
pins {
|
|
pinmux = <STM32F429_PB4_FUNC_TIM3_CH1>,
|
|
<STM32F429_PB5_FUNC_TIM3_CH2>;
|
|
};
|
|
};
|
|
|
|
i2c1_pins: i2c1@0 {
|
|
pins {
|
|
pinmux = <STM32F429_PB9_FUNC_I2C1_SDA>,
|
|
<STM32F429_PB6_FUNC_I2C1_SCL>;
|
|
bias-disable;
|
|
drive-open-drain;
|
|
slew-rate = <3>;
|
|
};
|
|
};
|
|
};
|
|
|
|
rcc: rcc@40023810 {
|
|
#reset-cells = <1>;
|
|
#clock-cells = <2>;
|
|
compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
|
|
reg = <0x40023800 0x400>;
|
|
clocks = <&clk_hse>, <&clk_i2s_ckin>;
|
|
st,syscfg = <&pwrcfg>;
|
|
assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
|
|
assigned-clock-rates = <1000000>;
|
|
};
|
|
|
|
dma1: dma-controller@40026000 {
|
|
compatible = "st,stm32-dma";
|
|
reg = <0x40026000 0x400>;
|
|
interrupts = <11>,
|
|
<12>,
|
|
<13>,
|
|
<14>,
|
|
<15>,
|
|
<16>,
|
|
<17>,
|
|
<47>;
|
|
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA1)>;
|
|
#dma-cells = <4>;
|
|
};
|
|
|
|
dma2: dma-controller@40026400 {
|
|
compatible = "st,stm32-dma";
|
|
reg = <0x40026400 0x400>;
|
|
interrupts = <56>,
|
|
<57>,
|
|
<58>,
|
|
<59>,
|
|
<60>,
|
|
<68>,
|
|
<69>,
|
|
<70>;
|
|
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2)>;
|
|
#dma-cells = <4>;
|
|
st,mem2mem;
|
|
};
|
|
|
|
mac: ethernet@40028000 {
|
|
compatible = "st,stm32-dwmac", "snps,dwmac-3.50a";
|
|
reg = <0x40028000 0x8000>;
|
|
reg-names = "stmmaceth";
|
|
interrupts = <61>;
|
|
interrupt-names = "macirq";
|
|
clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
|
|
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(ETHMAC)>,
|
|
<&rcc 0 STM32F4_AHB1_CLOCK(ETHMACTX)>,
|
|
<&rcc 0 STM32F4_AHB1_CLOCK(ETHMACRX)>;
|
|
st,syscon = <&syscfg 0x4>;
|
|
snps,pbl = <8>;
|
|
snps,mixed-burst;
|
|
status = "disabled";
|
|
};
|
|
|
|
usbotg_hs: usb@40040000 {
|
|
compatible = "snps,dwc2";
|
|
reg = <0x40040000 0x40000>;
|
|
interrupts = <77>;
|
|
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(OTGHS)>;
|
|
clock-names = "otg";
|
|
status = "disabled";
|
|
};
|
|
|
|
rng: rng@50060800 {
|
|
compatible = "st,stm32-rng";
|
|
reg = <0x50060800 0x400>;
|
|
interrupts = <80>;
|
|
clocks = <&rcc 0 STM32F4_AHB2_CLOCK(RNG)>;
|
|
|
|
};
|
|
};
|
|
};
|
|
|
|
&systick {
|
|
clocks = <&rcc 1 SYSTICK>;
|
|
status = "okay";
|
|
};
|