forked from Minki/linux
5d1f2d2c25
Netgear R8000 is a tri-band home router. It has three BCM43602 chipsets two of them for 5 GHz band. Both seem the same and their firmwares report the same set of channels. The problem is due to hardware / board design there are extra limitations that should be respected. First PHY should be used for U-NII-2 and U-NII-3. Third PHY should be used for U-NII-1. Using them in a different way may result in wireless not working or in noticeably reduced performance. Basic version of this info was provided by Broadcom employee, then it has been verified by me using original vendor firmware (which has limitations hardcoded in UI). This patch uses recently introduced ieee80211-freq-limit property to describe these limitations at DT level. Referencing PCIe devices in DT required specifying all related bridges. Below you can see (a bit complex) PCI tree from R8000 that explains all entries that I needed to put in DT. 0000:00:00.0 14e4:8012 Bridge Device └─ 0000:01:00.0 14e4:aa52 Network Controller 0001:00:00.0 14e4:8012 Bridge Device └─ 0001:01:00.0 10b5:8603 Bridge Device ├─ 0001:02:01.0 10b5:8603 Bridge Device │ └─ 0001:03:00.0 14e4:aa52 Network Controller ├─ 0001:02:02.0 10b5:8603 Bridge Device │ └─ 0001:04:00.0 14e4:aa52 Network Controller ├─ 0001:02:03.0 000d:0000 0x000000 ├─ 0001:02:04.0 000d:0000 0x000000 ├─ 0001:02:05.0 000d:0000 0x000000 ├─ 0001:02:06.0 000d:0000 0x000000 ├─ (...) ├─ 0001:02:1d.0 000d:0000 0x000000 ├─ 0001:02:1e.0 000d:0000 0x000000 └─ 0001:02:1f.0 000d:0000 0x000000 Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
379 lines
9.1 KiB
Plaintext
379 lines
9.1 KiB
Plaintext
/*
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* Broadcom BCM470X / BCM5301X ARM platform code.
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* Generic DTS part for all BCM53010, BCM53011, BCM53012, BCM53014, BCM53015,
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* BCM53016, BCM53017, BCM53018, BCM4707, BCM4708 and BCM4709 SoCs
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*
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* Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de>
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*
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* Licensed under the GNU/GPL. See COPYING for details.
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*/
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#include <dt-bindings/clock/bcm-nsp.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include "skeleton.dtsi"
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/ {
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interrupt-parent = <&gic>;
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chosen {
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stdout-path = &uart0;
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};
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chipcommonA {
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compatible = "simple-bus";
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ranges = <0x00000000 0x18000000 0x00001000>;
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#address-cells = <1>;
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#size-cells = <1>;
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uart0: serial@0300 {
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compatible = "ns16550";
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reg = <0x0300 0x100>;
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interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&iprocslow>;
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status = "disabled";
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};
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uart1: serial@0400 {
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compatible = "ns16550";
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reg = <0x0400 0x100>;
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interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&iprocslow>;
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status = "disabled";
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};
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};
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mpcore {
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compatible = "simple-bus";
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ranges = <0x00000000 0x19000000 0x00023000>;
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#address-cells = <1>;
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#size-cells = <1>;
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a9pll: arm_clk@00000 {
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#clock-cells = <0>;
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compatible = "brcm,nsp-armpll";
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clocks = <&osc>;
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reg = <0x00000 0x1000>;
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};
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scu@20000 {
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compatible = "arm,cortex-a9-scu";
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reg = <0x20000 0x100>;
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};
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timer@20200 {
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compatible = "arm,cortex-a9-global-timer";
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reg = <0x20200 0x100>;
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interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&periph_clk>;
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};
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local-timer@20600 {
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compatible = "arm,cortex-a9-twd-timer";
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reg = <0x20600 0x100>;
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&periph_clk>;
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};
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gic: interrupt-controller@21000 {
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compatible = "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0x21000 0x1000>,
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<0x20100 0x100>;
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};
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L2: cache-controller@22000 {
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compatible = "arm,pl310-cache";
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reg = <0x22000 0x1000>;
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cache-unified;
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arm,shared-override;
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prefetch-data = <1>;
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prefetch-instr = <1>;
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cache-level = <2>;
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};
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};
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pmu {
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compatible = "arm,cortex-a9-pmu";
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interrupts =
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<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
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};
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clocks {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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osc: oscillator {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <25000000>;
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};
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iprocmed: iprocmed {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
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clock-div = <2>;
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clock-mult = <1>;
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};
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iprocslow: iprocslow {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
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clock-div = <4>;
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clock-mult = <1>;
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};
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periph_clk: periph_clk {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&a9pll>;
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clock-div = <2>;
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clock-mult = <1>;
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};
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};
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usb2_phy: usb2-phy {
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compatible = "brcm,ns-usb2-phy";
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reg = <0x1800c000 0x1000>;
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reg-names = "dmu";
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#phy-cells = <0>;
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clocks = <&genpll BCM_NSP_GENPLL_USB_PHY_REF_CLK>;
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clock-names = "phy-ref-clk";
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};
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usb3_phy: usb3-phy {
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compatible = "brcm,ns-ax-usb3-phy";
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reg = <0x18105000 0x1000>, <0x18003000 0x1000>;
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reg-names = "dmp", "ccb-mii";
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#phy-cells = <0>;
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};
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axi@18000000 {
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compatible = "brcm,bus-axi";
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reg = <0x18000000 0x1000>;
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ranges = <0x00000000 0x18000000 0x00100000>;
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#address-cells = <1>;
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#size-cells = <1>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0x000fffff 0xffff>;
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interrupt-map =
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/* ChipCommon */
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<0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
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/* Switch Register Access Block */
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<0x00007000 0 &gic GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
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<0x00007000 1 &gic GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
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<0x00007000 2 &gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
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<0x00007000 3 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
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<0x00007000 4 &gic GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
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<0x00007000 5 &gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
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<0x00007000 6 &gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
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<0x00007000 7 &gic GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
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<0x00007000 8 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
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<0x00007000 9 &gic GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
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<0x00007000 10 &gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
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<0x00007000 11 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
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<0x00007000 12 &gic GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
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/* PCIe Controller 0 */
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<0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
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<0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
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<0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
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<0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
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<0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
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<0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
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/* PCIe Controller 1 */
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<0x00013000 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
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<0x00013000 1 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
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<0x00013000 2 &gic GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
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<0x00013000 3 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
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<0x00013000 4 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
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<0x00013000 5 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
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/* PCIe Controller 2 */
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<0x00014000 0 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
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<0x00014000 1 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
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<0x00014000 2 &gic GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
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<0x00014000 3 &gic GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
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<0x00014000 4 &gic GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
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<0x00014000 5 &gic GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
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/* USB 2.0 Controller */
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<0x00021000 0 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
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/* USB 3.0 Controller */
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<0x00023000 0 &gic GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
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/* Ethernet Controller 0 */
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<0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
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/* Ethernet Controller 1 */
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<0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
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/* Ethernet Controller 2 */
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<0x00026000 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
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/* Ethernet Controller 3 */
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<0x00027000 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
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/* NAND Controller */
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<0x00028000 0 &gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
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<0x00028000 1 &gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
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<0x00028000 2 &gic GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
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<0x00028000 3 &gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
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<0x00028000 4 &gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
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<0x00028000 5 &gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
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<0x00028000 6 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
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<0x00028000 7 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
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chipcommon: chipcommon@0 {
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reg = <0x00000000 0x1000>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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pcie0: pcie@12000 {
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reg = <0x00012000 0x1000>;
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};
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pcie1: pcie@13000 {
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reg = <0x00013000 0x1000>;
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};
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usb2: usb2@21000 {
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reg = <0x00021000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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interrupt-parent = <&gic>;
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ehci: ehci@21000 {
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#usb-cells = <0>;
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compatible = "generic-ehci";
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reg = <0x00021000 0x1000>;
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interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
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phys = <&usb2_phy>;
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};
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ohci: ohci@22000 {
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#usb-cells = <0>;
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compatible = "generic-ohci";
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reg = <0x00022000 0x1000>;
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interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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usb3: usb3@23000 {
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reg = <0x00023000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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interrupt-parent = <&gic>;
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xhci: xhci@23000 {
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#usb-cells = <0>;
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compatible = "generic-xhci";
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reg = <0x00023000 0x1000>;
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interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
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phys = <&usb3_phy>;
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phy-names = "usb";
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};
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};
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spi@29000 {
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reg = <0x00029000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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spi_nor: spi-nor@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <20000000>;
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linux,part-probe = "ofpart", "bcm47xxpart";
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status = "disabled";
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};
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};
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gmac0: ethernet@24000 {
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reg = <0x24000 0x800>;
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};
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gmac1: ethernet@25000 {
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reg = <0x25000 0x800>;
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};
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gmac2: ethernet@26000 {
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reg = <0x26000 0x800>;
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};
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gmac3: ethernet@27000 {
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reg = <0x27000 0x800>;
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};
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};
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lcpll0: lcpll0@1800c100 {
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#clock-cells = <1>;
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compatible = "brcm,nsp-lcpll0";
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reg = <0x1800c100 0x14>;
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clocks = <&osc>;
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clock-output-names = "lcpll0", "pcie_phy", "sdio",
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"ddr_phy";
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};
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genpll: genpll@1800c140 {
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#clock-cells = <1>;
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compatible = "brcm,nsp-genpll";
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reg = <0x1800c140 0x24>;
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clocks = <&osc>;
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clock-output-names = "genpll", "phy", "ethernetclk",
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"usbclk", "iprocfast", "sata1",
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"sata2";
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};
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srab: srab@18007000 {
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compatible = "brcm,bcm5301x-srab";
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reg = <0x18007000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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/* ports are defined in board DTS */
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};
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rng: rng@18004000 {
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compatible = "brcm,bcm5301x-rng";
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reg = <0x18004000 0x14>;
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};
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nand: nand@18028000 {
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compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand";
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reg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>;
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reg-names = "nand", "iproc-idm", "iproc-ext";
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interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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brcm,nand-has-wp;
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};
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};
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