afe2cf0840
Core DVFS support code is currently referencing clksel functionality, which is wrong. The m2 divisor has been implemented as a divider clock for a long time already, so replace the validrate check call with proper functionality. Core DVFS is currently not supported in the kernel so verifying this patch can be rather tricky, this should probably be fixed at some point. Signed-off-by: Tero Kristo <t-kristo@ti.com>
122 lines
3.2 KiB
C
122 lines
3.2 KiB
C
/*
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* OMAP34xx M2 divider clock code
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*
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* Copyright (C) 2007-2008 Texas Instruments, Inc.
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* Copyright (C) 2007-2010 Nokia Corporation
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*
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* Paul Walmsley
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* Jouni Högander
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*
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* Parts of this code are based on code written by
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* Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#undef DEBUG
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include "clock.h"
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#include "clock3xxx.h"
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#include "clock34xx.h"
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#include "sdrc.h"
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#include "sram.h"
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#define CYCLES_PER_MHZ 1000000
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/*
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* CORE DPLL (DPLL3) M2 divider rate programming functions
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*
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* These call into SRAM code to do the actual CM writes, since the SDRAM
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* is clocked from DPLL3.
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*/
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/**
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* omap3_core_dpll_m2_set_rate - set CORE DPLL M2 divider
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* @clk: struct clk * of DPLL to set
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* @rate: rounded target rate
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*
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* Program the DPLL M2 divider with the rounded target rate. Returns
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* -EINVAL upon error, or 0 upon success.
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*/
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int omap3_core_dpll_m2_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_hw_omap *clk = to_clk_hw_omap(hw);
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u32 new_div = 0;
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u32 unlock_dll = 0;
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u32 c;
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unsigned long validrate, sdrcrate, _mpurate;
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struct omap_sdrc_params *sdrc_cs0;
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struct omap_sdrc_params *sdrc_cs1;
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int ret;
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unsigned long clkrate;
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if (!clk || !rate)
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return -EINVAL;
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new_div = DIV_ROUND_UP(parent_rate, rate);
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validrate = parent_rate / new_div;
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if (validrate != rate)
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return -EINVAL;
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sdrcrate = __clk_get_rate(sdrc_ick_p);
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clkrate = __clk_get_rate(hw->clk);
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if (rate > clkrate)
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sdrcrate <<= ((rate / clkrate) >> 1);
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else
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sdrcrate >>= ((clkrate / rate) >> 1);
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ret = omap2_sdrc_get_params(sdrcrate, &sdrc_cs0, &sdrc_cs1);
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if (ret)
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return -EINVAL;
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if (sdrcrate < MIN_SDRC_DLL_LOCK_FREQ) {
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pr_debug("clock: will unlock SDRC DLL\n");
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unlock_dll = 1;
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}
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/*
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* XXX This only needs to be done when the CPU frequency changes
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*/
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_mpurate = __clk_get_rate(arm_fck_p) / CYCLES_PER_MHZ;
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c = (_mpurate << SDRC_MPURATE_SCALE) >> SDRC_MPURATE_BASE_SHIFT;
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c += 1; /* for safety */
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c *= SDRC_MPURATE_LOOPS;
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c >>= SDRC_MPURATE_SCALE;
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if (c == 0)
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c = 1;
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pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n",
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clkrate, validrate);
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pr_debug("clock: SDRC CS0 timing params used: RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
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sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
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sdrc_cs0->actim_ctrlb, sdrc_cs0->mr);
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if (sdrc_cs1)
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pr_debug("clock: SDRC CS1 timing params used: RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
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sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
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sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
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if (sdrc_cs1)
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omap3_configure_core_dpll(
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new_div, unlock_dll, c, rate > clkrate,
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sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
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sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
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sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
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sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
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else
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omap3_configure_core_dpll(
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new_div, unlock_dll, c, rate > clkrate,
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sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
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sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
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0, 0, 0, 0);
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return 0;
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}
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