linux/arch/arm64/mm
Mark Rutland 50e1881ddd arm64: mm: add code to safely replace TTBR1_EL1
If page tables are modified without suitable TLB maintenance, the ARM
architecture permits multiple TLB entries to be allocated for the same
VA. When this occurs, it is permitted that TLB conflict aborts are
raised in response to synchronous data/instruction accesses, and/or and
amalgamation of the TLB entries may be used as a result of a TLB lookup.

The presence of conflicting TLB entries may result in a variety of
behaviours detrimental to the system (e.g. erroneous physical addresses
may be used by I-cache fetches and/or page table walks). Some of these
cases may result in unexpected changes of hardware state, and/or result
in the (asynchronous) delivery of SError.

To avoid these issues, we must avoid situations where conflicting
entries may be allocated into TLBs. For user and module mappings we can
follow a strict break-before-make approach, but this cannot work for
modifications to the swapper page tables that cover the kernel text and
data.

Instead, this patch adds code which is intended to be executed from the
idmap, which can safely unmap the swapper page tables as it only
requires the idmap to be active. This enables us to uninstall the active
TTBR1_EL1 entry, invalidate TLBs, then install a new TTBR1_EL1 entry
without potentially unmapping code or data required for the sequence.
This avoids the risk of conflict, but requires that updates are staged
in a copy of the swapper page tables prior to being installed.

Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Tested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Tested-by: Jeremy Linton <jeremy.linton@arm.com>
Cc: Laura Abbott <labbott@fedoraproject.org>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-02-16 15:10:45 +00:00
..
cache.S arm64: Use PoU cache instr for I/D coherency 2015-12-17 11:07:13 +00:00
context.c arm64: mm: keep reserved ASIDs in sync with mm after multiple rollovers 2015-11-26 15:27:10 +00:00
copypage.c arm64: Defer dcache flush in __cpu_copy_user_page 2015-12-17 11:07:13 +00:00
dma-mapping.c arm64: add __init/__initdata section marker to some functions/variables 2015-12-02 12:17:11 +00:00
dump.c arm64: Fix an enum typo in mm/dump.c 2016-01-25 11:53:03 +00:00
extable.c arm64: MMU fault handling and page table management 2012-09-17 13:41:57 +01:00
fault.c arm64: mm: fix fault_info table xFSC decoding 2015-11-25 15:49:16 +00:00
flush.c arm64, thp: remove infrastructure for handling splitting PMDs 2016-01-15 17:56:32 -08:00
hugetlbpage.c arm64: hugetlb: add support for PTE contiguous bit 2015-12-21 17:26:00 +00:00
init.c Merge branch 'aarch64/efi' into aarch64/for-next/core 2015-12-15 10:59:03 +00:00
ioremap.c arm64: add ioremap physical address information 2015-01-23 15:29:06 +00:00
kasan_init.c arm64: kasan: ensure that the KASAN zero page is mapped read-only 2016-01-25 11:09:05 +00:00
Makefile arm64: add KASAN support 2015-10-12 17:46:36 +01:00
mm.h arm64: add better page protections to arm64 2015-01-22 14:54:29 +00:00
mmap.c arm64: mm: support ARCH_MMAP_RND_BITS 2016-01-14 16:00:49 -08:00
mmu.c arm64: unmap idmap earlier 2016-02-16 15:10:45 +00:00
pageattr.c arm64: allow vmalloc regions to be set with set_memory_* 2016-02-02 15:42:15 +00:00
pgd.c arm64: mm: move pgd_cache initialisation to pgtable_cache_init 2016-01-05 15:43:10 +00:00
proc-macros.S arm64: kernel: fix architected PMU registers unconditional access 2016-01-25 11:09:06 +00:00
proc.S arm64: mm: add code to safely replace TTBR1_EL1 2016-02-16 15:10:45 +00:00