forked from Minki/linux
b3ca9888f3
Create a separate reset driver that uses the reset operations in reset-simple. The reset driver for the SoCFPGA platform needs to register early in order to be able bring online timers that needed early in the kernel bootup. We do not need this early reset driver for Stratix10, because on arm64, Linux does not need the timers are that in reset. Linux is able to run just fine with the internal armv8 timer. Thus, we use a new binding "altr,stratix10-rst-mgr" for the Stratix10 platform. The Stratix10 platform will continue to use the reset-simple platform driver, while the 32-bit platforms(Cyclone5/Arria5/Arria10) will use the early reset driver. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> [p.zabel@pengutronix.de: fixed socfpga of_device_id in reset-simple] Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
89 lines
2.0 KiB
C
89 lines
2.0 KiB
C
// SPDX-License-Identifier: GPL-2.0
|
|
/*
|
|
* Copyright (C) 2018, Intel Corporation
|
|
* Copied from reset-sunxi.c
|
|
*/
|
|
|
|
#include <linux/err.h>
|
|
#include <linux/io.h>
|
|
#include <linux/init.h>
|
|
#include <linux/of.h>
|
|
#include <linux/of_address.h>
|
|
#include <linux/platform_device.h>
|
|
#include <linux/reset-controller.h>
|
|
#include <linux/slab.h>
|
|
#include <linux/spinlock.h>
|
|
#include <linux/types.h>
|
|
|
|
#include "reset-simple.h"
|
|
|
|
#define SOCFPGA_NR_BANKS 8
|
|
void __init socfpga_reset_init(void);
|
|
|
|
static int a10_reset_init(struct device_node *np)
|
|
{
|
|
struct reset_simple_data *data;
|
|
struct resource res;
|
|
resource_size_t size;
|
|
int ret;
|
|
u32 reg_offset = 0x10;
|
|
|
|
data = kzalloc(sizeof(*data), GFP_KERNEL);
|
|
if (!data)
|
|
return -ENOMEM;
|
|
|
|
ret = of_address_to_resource(np, 0, &res);
|
|
if (ret)
|
|
goto err_alloc;
|
|
|
|
size = resource_size(&res);
|
|
if (!request_mem_region(res.start, size, np->name)) {
|
|
ret = -EBUSY;
|
|
goto err_alloc;
|
|
}
|
|
|
|
data->membase = ioremap(res.start, size);
|
|
if (!data->membase) {
|
|
ret = -ENOMEM;
|
|
goto err_alloc;
|
|
}
|
|
|
|
if (of_property_read_u32(np, "altr,modrst-offset", ®_offset))
|
|
pr_warn("missing altr,modrst-offset property, assuming 0x10\n");
|
|
data->membase += reg_offset;
|
|
|
|
spin_lock_init(&data->lock);
|
|
|
|
data->rcdev.owner = THIS_MODULE;
|
|
data->rcdev.nr_resets = SOCFPGA_NR_BANKS * 32;
|
|
data->rcdev.ops = &reset_simple_ops;
|
|
data->rcdev.of_node = np;
|
|
data->status_active_low = true;
|
|
|
|
return reset_controller_register(&data->rcdev);
|
|
|
|
err_alloc:
|
|
kfree(data);
|
|
return ret;
|
|
};
|
|
|
|
/*
|
|
* These are the reset controller we need to initialize early on in
|
|
* our system, before we can even think of using a regular device
|
|
* driver for it.
|
|
* The controllers that we can register through the regular device
|
|
* model are handled by the simple reset driver directly.
|
|
*/
|
|
static const struct of_device_id socfpga_early_reset_dt_ids[] __initconst = {
|
|
{ .compatible = "altr,rst-mgr", },
|
|
{ /* sentinel */ },
|
|
};
|
|
|
|
void __init socfpga_reset_init(void)
|
|
{
|
|
struct device_node *np;
|
|
|
|
for_each_matching_node(np, socfpga_early_reset_dt_ids)
|
|
a10_reset_init(np);
|
|
}
|