forked from Minki/linux
af07484863
Bring Transparent HugePage support to ARM. The size of a transparent huge page depends on the normal page size. A transparent huge page is always represented as a pmd. If PAGE_SIZE is 4KB, THPs are 2MB. If PAGE_SIZE is 64KB, THPs are 512MB. Signed-off-by: Steve Capper <steve.capper@linaro.org> Acked-by: Catalin Marinas <catalin.marinas@arm.com>
125 lines
3.3 KiB
C
125 lines
3.3 KiB
C
/*
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* Based on arch/arm/include/asm/tlbflush.h
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*
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* Copyright (C) 1999-2003 Russell King
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* Copyright (C) 2012 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ASM_TLBFLUSH_H
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#define __ASM_TLBFLUSH_H
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#ifndef __ASSEMBLY__
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#include <linux/sched.h>
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#include <asm/cputype.h>
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extern void __cpu_flush_user_tlb_range(unsigned long, unsigned long, struct vm_area_struct *);
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extern void __cpu_flush_kern_tlb_range(unsigned long, unsigned long);
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extern struct cpu_tlb_fns cpu_tlb;
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/*
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* TLB Management
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* ==============
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*
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* The arch/arm64/mm/tlb.S files implement these methods.
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*
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* The TLB specific code is expected to perform whatever tests it needs
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* to determine if it should invalidate the TLB for each call. Start
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* addresses are inclusive and end addresses are exclusive; it is safe to
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* round these addresses down.
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*
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* flush_tlb_all()
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*
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* Invalidate the entire TLB.
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*
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* flush_tlb_mm(mm)
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*
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* Invalidate all TLB entries in a particular address space.
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* - mm - mm_struct describing address space
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*
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* flush_tlb_range(mm,start,end)
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*
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* Invalidate a range of TLB entries in the specified address
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* space.
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* - mm - mm_struct describing address space
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* - start - start address (may not be aligned)
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* - end - end address (exclusive, may not be aligned)
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*
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* flush_tlb_page(vaddr,vma)
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*
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* Invalidate the specified page in the specified address range.
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* - vaddr - virtual address (may not be aligned)
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* - vma - vma_struct describing address range
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*
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* flush_kern_tlb_page(kaddr)
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*
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* Invalidate the TLB entry for the specified page. The address
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* will be in the kernels virtual memory space. Current uses
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* only require the D-TLB to be invalidated.
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* - kaddr - Kernel virtual memory address
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*/
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static inline void flush_tlb_all(void)
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{
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dsb();
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asm("tlbi vmalle1is");
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dsb();
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isb();
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}
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static inline void flush_tlb_mm(struct mm_struct *mm)
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{
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unsigned long asid = (unsigned long)ASID(mm) << 48;
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dsb();
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asm("tlbi aside1is, %0" : : "r" (asid));
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dsb();
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}
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static inline void flush_tlb_page(struct vm_area_struct *vma,
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unsigned long uaddr)
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{
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unsigned long addr = uaddr >> 12 |
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((unsigned long)ASID(vma->vm_mm) << 48);
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dsb();
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asm("tlbi vae1is, %0" : : "r" (addr));
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dsb();
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}
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/*
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* Convert calls to our calling convention.
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*/
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#define flush_tlb_range(vma,start,end) __cpu_flush_user_tlb_range(start,end,vma)
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#define flush_tlb_kernel_range(s,e) __cpu_flush_kern_tlb_range(s,e)
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/*
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* On AArch64, the cache coherency is handled via the set_pte_at() function.
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*/
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static inline void update_mmu_cache(struct vm_area_struct *vma,
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unsigned long addr, pte_t *ptep)
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{
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/*
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* set_pte() does not have a DSB, so make sure that the page table
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* write is visible.
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*/
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dsb();
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}
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#define update_mmu_cache_pmd(vma, address, pmd) do { } while (0)
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#endif
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#endif
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