forked from Minki/linux
5c5bf25d4f
Introduce aarch64_insn_gen_{nop|branch_imm}() helper functions, which
will be used to implement jump label on ARM64.
Reviewed-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Jiang Liu <liuj97@gmail.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
109 lines
3.6 KiB
C
109 lines
3.6 KiB
C
/*
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* Copyright (C) 2013 Huawei Ltd.
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* Author: Jiang Liu <liuj97@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ASM_INSN_H
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#define __ASM_INSN_H
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#include <linux/types.h>
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/* A64 instructions are always 32 bits. */
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#define AARCH64_INSN_SIZE 4
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/*
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* ARM Architecture Reference Manual for ARMv8 Profile-A, Issue A.a
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* Section C3.1 "A64 instruction index by encoding":
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* AArch64 main encoding table
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* Bit position
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* 28 27 26 25 Encoding Group
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* 0 0 - - Unallocated
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* 1 0 0 - Data processing, immediate
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* 1 0 1 - Branch, exception generation and system instructions
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* - 1 - 0 Loads and stores
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* - 1 0 1 Data processing - register
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* 0 1 1 1 Data processing - SIMD and floating point
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* 1 1 1 1 Data processing - SIMD and floating point
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* "-" means "don't care"
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*/
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enum aarch64_insn_encoding_class {
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AARCH64_INSN_CLS_UNKNOWN, /* UNALLOCATED */
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AARCH64_INSN_CLS_DP_IMM, /* Data processing - immediate */
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AARCH64_INSN_CLS_DP_REG, /* Data processing - register */
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AARCH64_INSN_CLS_DP_FPSIMD, /* Data processing - SIMD and FP */
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AARCH64_INSN_CLS_LDST, /* Loads and stores */
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AARCH64_INSN_CLS_BR_SYS, /* Branch, exception generation and
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* system instructions */
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};
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enum aarch64_insn_hint_op {
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AARCH64_INSN_HINT_NOP = 0x0 << 5,
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AARCH64_INSN_HINT_YIELD = 0x1 << 5,
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AARCH64_INSN_HINT_WFE = 0x2 << 5,
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AARCH64_INSN_HINT_WFI = 0x3 << 5,
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AARCH64_INSN_HINT_SEV = 0x4 << 5,
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AARCH64_INSN_HINT_SEVL = 0x5 << 5,
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};
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enum aarch64_insn_imm_type {
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AARCH64_INSN_IMM_ADR,
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AARCH64_INSN_IMM_26,
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AARCH64_INSN_IMM_19,
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AARCH64_INSN_IMM_16,
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AARCH64_INSN_IMM_14,
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AARCH64_INSN_IMM_12,
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AARCH64_INSN_IMM_9,
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AARCH64_INSN_IMM_MAX
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};
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enum aarch64_insn_branch_type {
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AARCH64_INSN_BRANCH_NOLINK,
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AARCH64_INSN_BRANCH_LINK,
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};
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#define __AARCH64_INSN_FUNCS(abbr, mask, val) \
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static __always_inline bool aarch64_insn_is_##abbr(u32 code) \
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{ return (code & (mask)) == (val); } \
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static __always_inline u32 aarch64_insn_get_##abbr##_value(void) \
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{ return (val); }
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__AARCH64_INSN_FUNCS(b, 0xFC000000, 0x14000000)
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__AARCH64_INSN_FUNCS(bl, 0xFC000000, 0x94000000)
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__AARCH64_INSN_FUNCS(svc, 0xFFE0001F, 0xD4000001)
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__AARCH64_INSN_FUNCS(hvc, 0xFFE0001F, 0xD4000002)
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__AARCH64_INSN_FUNCS(smc, 0xFFE0001F, 0xD4000003)
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__AARCH64_INSN_FUNCS(brk, 0xFFE0001F, 0xD4200000)
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__AARCH64_INSN_FUNCS(hint, 0xFFFFF01F, 0xD503201F)
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#undef __AARCH64_INSN_FUNCS
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bool aarch64_insn_is_nop(u32 insn);
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int aarch64_insn_read(void *addr, u32 *insnp);
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int aarch64_insn_write(void *addr, u32 insn);
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enum aarch64_insn_encoding_class aarch64_get_insn_class(u32 insn);
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u32 aarch64_insn_encode_immediate(enum aarch64_insn_imm_type type,
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u32 insn, u64 imm);
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u32 aarch64_insn_gen_branch_imm(unsigned long pc, unsigned long addr,
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enum aarch64_insn_branch_type type);
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u32 aarch64_insn_gen_hint(enum aarch64_insn_hint_op op);
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u32 aarch64_insn_gen_nop(void);
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bool aarch64_insn_hotpatch_safe(u32 old_insn, u32 new_insn);
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int aarch64_insn_patch_text_nosync(void *addr, u32 insn);
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int aarch64_insn_patch_text_sync(void *addrs[], u32 insns[], int cnt);
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int aarch64_insn_patch_text(void *addrs[], u32 insns[], int cnt);
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#endif /* __ASM_INSN_H */
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