linux/drivers/gpu/drm/amd/display/dc/inc/hw
Meenakshikumar Somasundaram 4f8e37dbaf drm/amd/display: Support for DMUB AUX
[WHY]
To process AUX transactions with DMUB using inbox1 and outbox1 mail boxes.

[HOW]
1) Added inbox1 command DMUB_CMD__DP_AUX_ACCESS to issue AUX commands
   to DMUB in dc_process_dmub_aux_transfer_async(). DMUB processes AUX cmd
   with DCN and sends reply back in an outbox1 message triggering an
   outbox1 interrupt to driver.
2) In existing driver implementation, AUX commands are processed
   synchronously by configuring DCN reg. But in DMUB AUX, driver sends an
   inbox1 message and waits for a conditional variable (CV) which will be
   signaled by outbox1 ISR.
3) As the driver holds dal and dc locks while waiting for CV, the outbox1
   ISR is registered with noMutexWait set to true, which allows ISR to run
   and signal CV. This sets a constraint on ISR to not modify variables
   such as dc, dmub, etc.
4) Created dmub_outbox.c with dmub_enable_outbox_notification() to enable
   outbox1 mailbox.
5) New mailbox address ranges allocated for outbox1 of size DMUB_RB_SIZE.
   Created dmub functions for Outbox1: dmub_dcn20_setup_out_mailbox(),
   dmub_dcn20_get_outbox1_wptr() and dmub_dcn20_set_outbox1_rptr().
6) Added functions dc_stat_get_dmub_notification() and
   dmub_srv_stat_get_notification() to retrieve Outbox1 message.
7) Currently, DMUB doesn't opens DDC in AUX mode before issuing AUX
   transaction. A workaround is added in dce_aux_transfer_dmub_raw() to
   open in DDC in AUX mode for every AUX transaction.
8) Added dc debug option enable_dmub_aux_for_legacy_ddc enable/disable
   DMUB AUX. This debug option is checked dce_aux_transfer_with_retries()
   to select the method to process AUX transactions.

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-02 14:05:41 -05:00
..
abm.h
audio.h
aux_engine.h drm/amd/display: Support for DMUB AUX 2021-03-02 14:05:41 -05:00
clk_mgr_internal.h drm/amd/display: Simplify bool comparison 2021-02-09 15:49:42 -05:00
clk_mgr.h drm/amdgpu: fold CONFIG_DRM_AMD_DC_DCN3* into CONFIG_DRM_AMD_DC_DCN (v3) 2020-11-04 17:11:37 -05:00
dccg.h
dchubbub.h drm/amd/display: Populate hostvm parameter before DML calculation 2020-11-16 12:18:44 -05:00
dmcu.h drm/amd/display: Add Freesync HDMI support to DMCU 2021-02-02 12:11:41 -05:00
dpp.h drm/amd/display/dc/inc/hw/dpp: Mark 'dpp_input_csc_matrix' as __maybe_unused 2020-12-01 16:04:45 -05:00
dsc.h drm/amd/display: Rename bytes_pp to the correct bits_pp 2020-07-27 16:23:21 -04:00
dwb.h drm/amdgpu: fold CONFIG_DRM_AMD_DC_DCN3* into CONFIG_DRM_AMD_DC_DCN (v3) 2020-11-04 17:11:37 -05:00
gpio.h
hubp.h drm/amd/display: Interfaces for hubp blank and soft reset 2020-12-23 15:01:24 -05:00
hw_shared.h drm/amd/display: Move common speakersToChannels definition to hw_shared.h 2020-11-10 14:25:15 -05:00
ipp.h
link_encoder.h drm/amd/display: Define PSR ERROR Status bit VSC_SDP 2020-10-26 13:29:27 -04:00
mcif_wb.h drm/amdgpu: fold CONFIG_DRM_AMD_DC_DCN3* into CONFIG_DRM_AMD_DC_DCN (v3) 2020-11-04 17:11:37 -05:00
mem_input.h
mpc.h drm/amd/display: add getter routine to retrieve mpcc mux 2020-12-23 15:02:55 -05:00
opp.h drm/amd/display: Raise DPG height during timing synchronization 2020-10-26 13:29:21 -04:00
panel_cntl.h drm/amd/display: Add read backlight interface 2020-08-17 14:08:12 -04:00
stream_encoder.h drm/amdgpu: fold CONFIG_DRM_AMD_DC_DCN3* into CONFIG_DRM_AMD_DC_DCN (v3) 2020-11-04 17:11:37 -05:00
timing_generator.h drm/amd/display: Synchronize displays with different timings 2021-02-22 18:05:48 -05:00
transform.h
vmid.h