linux/arch/openrisc
Jan Henrik Weinstock 4ee93d80ad openrisc: add cacheflush support to fix icache aliasing
On OpenRISC the icache does not snoop data stores.  This can cause
aliasing as reported by Jan. This patch fixes the issue to ensure icache
is properly synchronized when code is written to memory.  It supports both
SMP and UP flushing.

This supports dcache flush as well for architectures that do not support
write-through caches; most OpenRISC implementations do implement
write-through cache however. Dcache flushes are done only on a single
core as OpenRISC dcaches all support snooping of bus stores.

Signed-off-by: Jan Henrik Weinstock <jan.weinstock@ice.rwth-aachen.de>
[shorne@gmail.com: Squashed patches and wrote commit message]
Signed-off-by: Stafford Horne <shorne@gmail.com>
2017-11-03 14:01:15 +09:00
..
boot/dts openrisc: dts: or1ksim: Add stdout-path 2017-10-30 21:37:51 +09:00
configs openrisc: defconfig: Cleanup from old Kconfig options 2017-07-08 04:35:30 +09:00
include openrisc: add cacheflush support to fix icache aliasing 2017-11-03 14:01:15 +09:00
kernel openrisc: add cacheflush support to fix icache aliasing 2017-11-03 14:01:15 +09:00
lib openrisc: initial SMP support 2017-11-03 14:01:13 +09:00
mm openrisc: add cacheflush support to fix icache aliasing 2017-11-03 14:01:15 +09:00
Kconfig openrisc: add cacheflush support to fix icache aliasing 2017-11-03 14:01:15 +09:00
Makefile openrisc: Makefile: append "-D__linux__" to KBUILD_CFLAGS 2013-11-05 16:14:47 +01:00