Christian König 4ed108352d drm/radeon: put UVD PLLs in bypass mode ... Just power down the PLL when we get a VCLK or DCLK of zero. Enabling the bypass mode early should also allow us to switch UVD clocks on the fly. Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2013-04-22 10:39:16 -04:00
..
drm	drm/radeon: put UVD PLLs in bypass mode	2013-04-22 10:39:16 -04:00
host1x	drm/tegra: don't depend on OF	2013-04-22 12:40:56 +02:00
vga	fbcon: fix locking harder	2013-02-08 12:02:43 +10:00
Makefile	gpu: host1x: Add host1x driver	2013-04-22 12:32:40 +02:00