forked from Minki/linux
92c9e0c780
The Parallella board comes with a U-Boot bootloader that loads one of two predefined FPGA bitstreams before booting the kernel. Both define an AXI interface to the on-board Epiphany processor. Enable clocks FCLK0..FCLK3 for the Programmable Logic by default. Otherwise accessing, e.g., the ESYSRESET register freezes the board, as seen with the Epiphany SDK tools e-reset and e-hw-rev, using /dev/mem. Cc: <stable@vger.kernel.org> # 3.17.x Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Olof Johansson <olof@lixom.net>
90 lines
1.8 KiB
Plaintext
90 lines
1.8 KiB
Plaintext
/*
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* Copyright (c) 2014 SUSE LINUX Products GmbH
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*
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* Derived from zynq-zed.dts:
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*
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* Copyright (C) 2011 Xilinx
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* Copyright (C) 2012 National Instruments Corp.
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* Copyright (C) 2013 Xilinx
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/dts-v1/;
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/include/ "zynq-7000.dtsi"
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/ {
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model = "Adapteva Parallella Board";
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compatible = "adapteva,parallella", "xlnx,zynq-7000";
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memory {
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device_type = "memory";
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reg = <0x0 0x40000000>;
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};
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chosen {
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bootargs = "console=ttyPS0,115200 earlyprintk root=/dev/mmcblk0p2 rootfstype=ext4 rw rootwait";
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linux,stdout-path = "/amba/serial@e0001000";
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};
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};
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&clkc {
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fclk-enable = <0xf>;
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};
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&gem0 {
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status = "okay";
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phy-mode = "rgmii-id";
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phy-handle = <ðernet_phy>;
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ethernet_phy: ethernet-phy@0 {
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/* Marvell 88E1318 */
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compatible = "ethernet-phy-id0141.0e90",
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"ethernet-phy-ieee802.3-c22";
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reg = <0>;
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marvell,reg-init = <0x3 0x10 0xff00 0x1e>,
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<0x3 0x11 0xfff0 0xa>;
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};
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};
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&i2c0 {
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status = "okay";
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isl9305: isl9305@68 {
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compatible = "isl,isl9305";
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reg = <0x68>;
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regulators {
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dcd1 {
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regulator-name = "VDD_DSP";
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regulator-always-on;
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};
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dcd2 {
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regulator-name = "1P35V";
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regulator-always-on;
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};
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ldo1 {
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regulator-name = "VDD_ADJ";
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};
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ldo2 {
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regulator-name = "VDD_GPIO";
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regulator-always-on;
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};
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};
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};
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};
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&sdhci1 {
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status = "okay";
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};
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&uart1 {
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status = "okay";
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};
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