forked from Minki/linux
66f1376269
fiji and polaris can share same setup_pwr_virus function. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
376 lines
14 KiB
C
376 lines
14 KiB
C
/*
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* Copyright 2015 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "pp_debug.h"
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#include "smumgr.h"
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#include "smu74.h"
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#include "smu_ucode_xfer_vi.h"
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#include "polaris10_smumgr.h"
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#include "smu74_discrete.h"
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#include "smu/smu_7_1_3_d.h"
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#include "smu/smu_7_1_3_sh_mask.h"
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#include "gmc/gmc_8_1_d.h"
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#include "gmc/gmc_8_1_sh_mask.h"
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#include "oss/oss_3_0_d.h"
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#include "gca/gfx_8_0_d.h"
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#include "bif/bif_5_0_d.h"
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#include "bif/bif_5_0_sh_mask.h"
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#include "ppatomctrl.h"
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#include "cgs_common.h"
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#include "polaris10_smc.h"
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#include "smu7_ppsmc.h"
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#include "smu7_smumgr.h"
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#define PPPOLARIS10_TARGETACTIVITY_DFLT 50
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static const SMU74_Discrete_GraphicsLevel avfs_graphics_level_polaris10[8] = {
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/* Min pcie DeepSleep Activity CgSpll CgSpll CcPwr CcPwr Sclk Enabled Enabled Voltage Power */
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/* Voltage, DpmLevel, DivId, Level, FuncCntl3, FuncCntl4, DynRm, DynRm1 Did, Padding,ForActivity, ForThrottle, UpHyst, DownHyst, DownHyst, Throttle */
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{ 0x100ea446, 0x00, 0x03, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x30750000, 0x3000, 0, 0x2600, 0, 0, 0x0004, 0x8f02, 0xffff, 0x2f00, 0x300e, 0x2700 } },
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{ 0x400ea446, 0x01, 0x04, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x409c0000, 0x2000, 0, 0x1e00, 1, 1, 0x0004, 0x8300, 0xffff, 0x1f00, 0xcb5e, 0x1a00 } },
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{ 0x740ea446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x50c30000, 0x2800, 0, 0x2000, 1, 1, 0x0004, 0x0c02, 0xffff, 0x2700, 0x6433, 0x2100 } },
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{ 0xa40ea446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x60ea0000, 0x3000, 0, 0x2600, 1, 1, 0x0004, 0x8f02, 0xffff, 0x2f00, 0x300e, 0x2700 } },
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{ 0xd80ea446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x70110100, 0x3800, 0, 0x2c00, 1, 1, 0x0004, 0x1203, 0xffff, 0x3600, 0xc9e2, 0x2e00 } },
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{ 0x3c0fa446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x80380100, 0x2000, 0, 0x1e00, 2, 1, 0x0004, 0x8300, 0xffff, 0x1f00, 0xcb5e, 0x1a00 } },
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{ 0x6c0fa446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x905f0100, 0x2400, 0, 0x1e00, 2, 1, 0x0004, 0x8901, 0xffff, 0x2300, 0x314c, 0x1d00 } },
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{ 0xa00fa446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0xa0860100, 0x2800, 0, 0x2000, 2, 1, 0x0004, 0x0c02, 0xffff, 0x2700, 0x6433, 0x2100 } }
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};
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static const SMU74_Discrete_MemoryLevel avfs_memory_level_polaris10 = {
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0x100ea446, 0, 0x30750000, 0x01, 0x01, 0x01, 0x00, 0x00, 0x64, 0x00, 0x00, 0x1f00, 0x00, 0x00};
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static int polaris10_perform_btc(struct pp_hwmgr *hwmgr)
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{
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int result = 0;
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struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
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if (0 != smu_data->avfs.avfs_btc_param) {
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if (0 != smu7_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_PerformBtc, smu_data->avfs.avfs_btc_param)) {
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pr_info("[AVFS][SmuPolaris10_PerformBtc] PerformBTC SMU msg failed");
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result = -1;
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}
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}
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if (smu_data->avfs.avfs_btc_param > 1) {
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/* Soft-Reset to reset the engine before loading uCode */
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/* halt */
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cgs_write_register(hwmgr->device, mmCP_MEC_CNTL, 0x50000000);
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/* reset everything */
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cgs_write_register(hwmgr->device, mmGRBM_SOFT_RESET, 0xffffffff);
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cgs_write_register(hwmgr->device, mmGRBM_SOFT_RESET, 0);
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}
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return result;
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}
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static int polaris10_setup_graphics_level_structure(struct pp_hwmgr *hwmgr)
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{
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uint32_t vr_config;
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uint32_t dpm_table_start;
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uint16_t u16_boot_mvdd;
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uint32_t graphics_level_address, vr_config_address, graphics_level_size;
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graphics_level_size = sizeof(avfs_graphics_level_polaris10);
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u16_boot_mvdd = PP_HOST_TO_SMC_US(1300 * VOLTAGE_SCALE);
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PP_ASSERT_WITH_CODE(0 == smu7_read_smc_sram_dword(hwmgr,
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SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, DpmTable),
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&dpm_table_start, 0x40000),
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"[AVFS][Polaris10_SetupGfxLvlStruct] SMU could not communicate starting address of DPM table",
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return -1);
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/* Default value for VRConfig = VR_MERGED_WITH_VDDC + VR_STATIC_VOLTAGE(VDDCI) */
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vr_config = 0x01000500; /* Real value:0x50001 */
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vr_config_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, VRConfig);
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PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, vr_config_address,
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(uint8_t *)&vr_config, sizeof(uint32_t), 0x40000),
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"[AVFS][Polaris10_SetupGfxLvlStruct] Problems copying VRConfig value over to SMC",
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return -1);
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graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, GraphicsLevel);
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PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, graphics_level_address,
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(uint8_t *)(&avfs_graphics_level_polaris10),
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graphics_level_size, 0x40000),
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"[AVFS][Polaris10_SetupGfxLvlStruct] Copying of SCLK DPM table failed!",
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return -1);
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graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, MemoryLevel);
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PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, graphics_level_address,
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(uint8_t *)(&avfs_memory_level_polaris10), sizeof(avfs_memory_level_polaris10), 0x40000),
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"[AVFS][Polaris10_SetupGfxLvlStruct] Copying of MCLK DPM table failed!",
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return -1);
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/* MVDD Boot value - neccessary for getting rid of the hang that occurs during Mclk DPM enablement */
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graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, BootMVdd);
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PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, graphics_level_address,
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(uint8_t *)(&u16_boot_mvdd), sizeof(u16_boot_mvdd), 0x40000),
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"[AVFS][Polaris10_SetupGfxLvlStruct] Copying of DPM table failed!",
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return -1);
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return 0;
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}
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static int
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polaris10_avfs_event_mgr(struct pp_hwmgr *hwmgr, bool SMU_VFT_INTACT)
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{
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struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
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switch (smu_data->avfs.avfs_btc_status) {
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case AVFS_BTC_COMPLETED_PREVIOUSLY:
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break;
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case AVFS_BTC_BOOT: /* Cold Boot State - Post SMU Start */
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smu_data->avfs.avfs_btc_status = AVFS_BTC_DPMTABLESETUP_FAILED;
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PP_ASSERT_WITH_CODE(0 == polaris10_setup_graphics_level_structure(hwmgr),
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"[AVFS][Polaris10_AVFSEventMgr] Could not Copy Graphics Level table over to SMU",
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return -EINVAL);
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if (smu_data->avfs.avfs_btc_param > 1) {
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pr_info("[AVFS][Polaris10_AVFSEventMgr] AC BTC has not been successfully verified on Fiji. There may be in this setting.");
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smu_data->avfs.avfs_btc_status = AVFS_BTC_VIRUS_FAIL;
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PP_ASSERT_WITH_CODE(0 == smu7_setup_pwr_virus(hwmgr),
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"[AVFS][Polaris10_AVFSEventMgr] Could not setup Pwr Virus for AVFS ",
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return -EINVAL);
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}
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smu_data->avfs.avfs_btc_status = AVFS_BTC_FAILED;
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PP_ASSERT_WITH_CODE(0 == polaris10_perform_btc(hwmgr),
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"[AVFS][Polaris10_AVFSEventMgr] Failure at SmuPolaris10_PerformBTC. AVFS Disabled",
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return -EINVAL);
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smu_data->avfs.avfs_btc_status = AVFS_BTC_ENABLEAVFS;
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break;
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case AVFS_BTC_DISABLED:
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case AVFS_BTC_ENABLEAVFS:
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case AVFS_BTC_NOTSUPPORTED:
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break;
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default:
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pr_err("AVFS failed status is %x!\n", smu_data->avfs.avfs_btc_status);
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break;
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}
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return 0;
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}
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static int polaris10_start_smu_in_protection_mode(struct pp_hwmgr *hwmgr)
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{
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int result = 0;
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/* Wait for smc boot up */
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/* PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND, RCU_UC_EVENTS, boot_seq_done, 0) */
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/* Assert reset */
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PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
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SMC_SYSCON_RESET_CNTL, rst_reg, 1);
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result = smu7_upload_smu_firmware_image(hwmgr);
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if (result != 0)
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return result;
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/* Clear status */
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cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMU_STATUS, 0);
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PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
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SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
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/* De-assert reset */
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PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
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SMC_SYSCON_RESET_CNTL, rst_reg, 0);
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PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, RCU_UC_EVENTS, INTERRUPTS_ENABLED, 1);
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/* Call Test SMU message with 0x20000 offset to trigger SMU start */
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smu7_send_msg_to_smc_offset(hwmgr);
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/* Wait done bit to be set */
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/* Check pass/failed indicator */
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PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND, SMU_STATUS, SMU_DONE, 0);
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if (1 != PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
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SMU_STATUS, SMU_PASS))
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PP_ASSERT_WITH_CODE(false, "SMU Firmware start failed!", return -1);
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cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixFIRMWARE_FLAGS, 0);
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PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
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SMC_SYSCON_RESET_CNTL, rst_reg, 1);
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PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
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SMC_SYSCON_RESET_CNTL, rst_reg, 0);
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/* Wait for firmware to initialize */
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PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
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return result;
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}
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static int polaris10_start_smu_in_non_protection_mode(struct pp_hwmgr *hwmgr)
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{
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int result = 0;
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/* wait for smc boot up */
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PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND, RCU_UC_EVENTS, boot_seq_done, 0);
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/* Clear firmware interrupt enable flag */
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/* PHM_WRITE_VFPF_INDIRECT_FIELD(pSmuMgr, SMC_IND, SMC_SYSCON_MISC_CNTL, pre_fetcher_en, 1); */
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cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
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ixFIRMWARE_FLAGS, 0);
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PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
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SMC_SYSCON_RESET_CNTL,
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rst_reg, 1);
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result = smu7_upload_smu_firmware_image(hwmgr);
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if (result != 0)
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return result;
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/* Set smc instruct start point at 0x0 */
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smu7_program_jump_on_start(hwmgr);
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PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
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SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
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PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
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SMC_SYSCON_RESET_CNTL, rst_reg, 0);
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/* Wait for firmware to initialize */
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PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND,
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FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
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return result;
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}
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static int polaris10_start_smu(struct pp_hwmgr *hwmgr)
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{
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int result = 0;
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struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
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bool SMU_VFT_INTACT;
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/* Only start SMC if SMC RAM is not running */
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if (!smu7_is_smc_ram_running(hwmgr)) {
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SMU_VFT_INTACT = false;
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smu_data->protected_mode = (uint8_t) (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_MODE));
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smu_data->smu7_data.security_hard_key = (uint8_t) (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_SEL));
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/* Check if SMU is running in protected mode */
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if (smu_data->protected_mode == 0) {
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result = polaris10_start_smu_in_non_protection_mode(hwmgr);
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} else {
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result = polaris10_start_smu_in_protection_mode(hwmgr);
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/* If failed, try with different security Key. */
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if (result != 0) {
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smu_data->smu7_data.security_hard_key ^= 1;
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cgs_rel_firmware(hwmgr->device, CGS_UCODE_ID_SMU);
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result = polaris10_start_smu_in_protection_mode(hwmgr);
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}
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}
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if (result != 0)
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PP_ASSERT_WITH_CODE(0, "Failed to load SMU ucode.", return result);
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polaris10_avfs_event_mgr(hwmgr, true);
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} else
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SMU_VFT_INTACT = true; /*Driver went offline but SMU was still alive and contains the VFT table */
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polaris10_avfs_event_mgr(hwmgr, SMU_VFT_INTACT);
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/* Setup SoftRegsStart here for register lookup in case DummyBackEnd is used and ProcessFirmwareHeader is not executed */
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smu7_read_smc_sram_dword(hwmgr, SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, SoftRegisters),
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&(smu_data->smu7_data.soft_regs_start), 0x40000);
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result = smu7_request_smu_load_fw(hwmgr);
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return result;
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}
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static bool polaris10_is_hw_avfs_present(struct pp_hwmgr *hwmgr)
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{
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uint32_t efuse;
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efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMU_EFUSE_0 + (49*4));
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efuse &= 0x00000001;
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if (efuse)
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return true;
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return false;
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}
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static int polaris10_smu_init(struct pp_hwmgr *hwmgr)
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{
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struct polaris10_smumgr *smu_data;
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int i;
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smu_data = kzalloc(sizeof(struct polaris10_smumgr), GFP_KERNEL);
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if (smu_data == NULL)
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return -ENOMEM;
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hwmgr->smu_backend = smu_data;
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if (smu7_init(hwmgr))
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return -EINVAL;
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for (i = 0; i < SMU74_MAX_LEVELS_GRAPHICS; i++)
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smu_data->activity_target[i] = PPPOLARIS10_TARGETACTIVITY_DFLT;
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return 0;
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}
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const struct pp_smumgr_func polaris10_smu_funcs = {
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.smu_init = polaris10_smu_init,
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.smu_fini = smu7_smu_fini,
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.start_smu = polaris10_start_smu,
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.check_fw_load_finish = smu7_check_fw_load_finish,
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.request_smu_load_fw = smu7_reload_firmware,
|
|
.request_smu_load_specific_fw = NULL,
|
|
.send_msg_to_smc = smu7_send_msg_to_smc,
|
|
.send_msg_to_smc_with_parameter = smu7_send_msg_to_smc_with_parameter,
|
|
.download_pptable_settings = NULL,
|
|
.upload_pptable_settings = NULL,
|
|
.update_smc_table = polaris10_update_smc_table,
|
|
.get_offsetof = polaris10_get_offsetof,
|
|
.process_firmware_header = polaris10_process_firmware_header,
|
|
.init_smc_table = polaris10_init_smc_table,
|
|
.update_sclk_threshold = polaris10_update_sclk_threshold,
|
|
.thermal_avfs_enable = polaris10_thermal_avfs_enable,
|
|
.thermal_setup_fan_table = polaris10_thermal_setup_fan_table,
|
|
.populate_all_graphic_levels = polaris10_populate_all_graphic_levels,
|
|
.populate_all_memory_levels = polaris10_populate_all_memory_levels,
|
|
.get_mac_definition = polaris10_get_mac_definition,
|
|
.is_dpm_running = polaris10_is_dpm_running,
|
|
.populate_requested_graphic_levels = polaris10_populate_requested_graphic_levels,
|
|
.is_hw_avfs_present = polaris10_is_hw_avfs_present,
|
|
};
|