forked from Minki/linux
0bbd0d4be8
This uses values from the MMCRA, SIAR and SDAR registers on powerpc to supply more precise information for overflow events, including a data address when PERF_RECORD_ADDR is specified. Since POWER6 uses different bit positions in MMCRA from earlier processors, this converts the struct power_pmu limited_pmc5_6 field, which only had 0/1 values, into a flags field and defines bit values for its previous use (PPMU_LIMITED_PMC5_6) and a new flag (PPMU_ALT_SIPR) to indicate that the processor uses the POWER6 bit positions rather than the earlier positions. It also adds definitions in reg.h for the new and old positions of the bit that indicates that the SIAR and SDAR values come from the same instruction. For the data address, the SDAR value is supplied if we are not doing instruction sampling. In that case there is no guarantee that the address given in the PERF_RECORD_ADDR subrecord will correspond to the instruction whose address is given in the PERF_RECORD_IP subrecord. If instruction sampling is enabled (e.g. because this counter is counting a marked instruction event), then we only supply the SDAR value for the PERF_RECORD_ADDR subrecord if it corresponds to the instruction whose address is in the PERF_RECORD_IP subrecord. Otherwise we supply 0. [ Impact: support more PMU hardware features on PowerPC ] Signed-off-by: Paul Mackerras <paulus@samba.org> Acked-by: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Corey Ashford <cjashfor@linux.vnet.ibm.com> Cc: Arnaldo Carvalho de Melo <acme@redhat.com> LKML-Reference: <18955.37028.48861.555309@drongo.ozlabs.ibm.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
96 lines
3.6 KiB
C
96 lines
3.6 KiB
C
/*
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* Performance counter support - PowerPC-specific definitions.
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*
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* Copyright 2008-2009 Paul Mackerras, IBM Corporation.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/types.h>
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#define MAX_HWCOUNTERS 8
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#define MAX_EVENT_ALTERNATIVES 8
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#define MAX_LIMITED_HWCOUNTERS 2
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/*
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* This struct provides the constants and functions needed to
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* describe the PMU on a particular POWER-family CPU.
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*/
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struct power_pmu {
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int n_counter;
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int max_alternatives;
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u64 add_fields;
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u64 test_adder;
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int (*compute_mmcr)(u64 events[], int n_ev,
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unsigned int hwc[], u64 mmcr[]);
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int (*get_constraint)(u64 event, u64 *mskp, u64 *valp);
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int (*get_alternatives)(u64 event, unsigned int flags,
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u64 alt[]);
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void (*disable_pmc)(unsigned int pmc, u64 mmcr[]);
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int (*limited_pmc_event)(u64 event);
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u32 flags;
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int n_generic;
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int *generic_events;
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};
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extern struct power_pmu *ppmu;
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/*
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* Values for power_pmu.flags
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*/
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#define PPMU_LIMITED_PMC5_6 1 /* PMC5/6 have limited function */
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#define PPMU_ALT_SIPR 2 /* uses alternate posn for SIPR/HV */
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/*
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* Values for flags to get_alternatives()
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*/
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#define PPMU_LIMITED_PMC_OK 1 /* can put this on a limited PMC */
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#define PPMU_LIMITED_PMC_REQD 2 /* have to put this on a limited PMC */
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#define PPMU_ONLY_COUNT_RUN 4 /* only counting in run state */
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struct pt_regs;
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extern unsigned long perf_misc_flags(struct pt_regs *regs);
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#define perf_misc_flags(regs) perf_misc_flags(regs)
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extern unsigned long perf_instruction_pointer(struct pt_regs *regs);
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/*
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* The power_pmu.get_constraint function returns a 64-bit value and
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* a 64-bit mask that express the constraints between this event and
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* other events.
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*
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* The value and mask are divided up into (non-overlapping) bitfields
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* of three different types:
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*
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* Select field: this expresses the constraint that some set of bits
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* in MMCR* needs to be set to a specific value for this event. For a
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* select field, the mask contains 1s in every bit of the field, and
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* the value contains a unique value for each possible setting of the
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* MMCR* bits. The constraint checking code will ensure that two events
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* that set the same field in their masks have the same value in their
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* value dwords.
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*
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* Add field: this expresses the constraint that there can be at most
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* N events in a particular class. A field of k bits can be used for
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* N <= 2^(k-1) - 1. The mask has the most significant bit of the field
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* set (and the other bits 0), and the value has only the least significant
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* bit of the field set. In addition, the 'add_fields' and 'test_adder'
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* in the struct power_pmu for this processor come into play. The
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* add_fields value contains 1 in the LSB of the field, and the
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* test_adder contains 2^(k-1) - 1 - N in the field.
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*
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* NAND field: this expresses the constraint that you may not have events
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* in all of a set of classes. (For example, on PPC970, you can't select
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* events from the FPU, ISU and IDU simultaneously, although any two are
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* possible.) For N classes, the field is N+1 bits wide, and each class
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* is assigned one bit from the least-significant N bits. The mask has
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* only the most-significant bit set, and the value has only the bit
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* for the event's class set. The test_adder has the least significant
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* bit set in the field.
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*
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* If an event is not subject to the constraint expressed by a particular
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* field, then it will have 0 in both the mask and value for that field.
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*/
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