forked from Minki/linux
f16dab981a
Add basic support for the PCIe PHB and enable the ULI bridge. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
371 lines
8.9 KiB
C
371 lines
8.9 KiB
C
/*
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* MPC8544 DS Board Setup
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*
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* Author Xianghua Xiao (x.xiao@freescale.com)
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* Roy Zang <tie-fei.zang@freescale.com>
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* - Add PCI/PCI Exprees support
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* Copyright 2007 Freescale Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/stddef.h>
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/kdev_t.h>
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#include <linux/delay.h>
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#include <linux/seq_file.h>
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#include <linux/interrupt.h>
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#include <asm/system.h>
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#include <asm/time.h>
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#include <asm/machdep.h>
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#include <asm/pci-bridge.h>
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#include <asm/mpc85xx.h>
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#include <mm/mmu_decl.h>
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#include <asm/prom.h>
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#include <asm/udbg.h>
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#include <asm/mpic.h>
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#include <asm/i8259.h>
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#include <sysdev/fsl_soc.h>
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#include <sysdev/fsl_pci.h>
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#include "mpc85xx.h"
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#undef DEBUG
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#ifdef DEBUG
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#define DBG(fmt, args...) printk(KERN_ERR "%s: " fmt, __FUNCTION__, ## args)
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#else
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#define DBG(fmt, args...)
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#endif
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#ifdef CONFIG_PPC_I8259
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static void mpc8544_8259_cascade(unsigned int irq, struct irq_desc *desc)
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{
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unsigned int cascade_irq = i8259_irq();
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if (cascade_irq != NO_IRQ) {
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generic_handle_irq(cascade_irq);
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}
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desc->chip->eoi(irq);
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}
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#endif /* CONFIG_PPC_I8259 */
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void __init mpc8544_ds_pic_init(void)
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{
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struct mpic *mpic;
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struct resource r;
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struct device_node *np = NULL;
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#ifdef CONFIG_PPC_I8259
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struct device_node *cascade_node = NULL;
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int cascade_irq;
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#endif
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np = of_find_node_by_type(np, "open-pic");
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if (np == NULL) {
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printk(KERN_ERR "Could not find open-pic node\n");
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return;
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}
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if (of_address_to_resource(np, 0, &r)) {
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printk(KERN_ERR "Failed to map mpic register space\n");
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of_node_put(np);
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return;
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}
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mpic = mpic_alloc(np, r.start,
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MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
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0, 256, " OpenPIC ");
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BUG_ON(mpic == NULL);
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mpic_init(mpic);
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#ifdef CONFIG_PPC_I8259
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/* Initialize the i8259 controller */
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for_each_node_by_type(np, "interrupt-controller")
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if (of_device_is_compatible(np, "chrp,iic")) {
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cascade_node = np;
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break;
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}
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if (cascade_node == NULL) {
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printk(KERN_DEBUG "Could not find i8259 PIC\n");
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return;
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}
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cascade_irq = irq_of_parse_and_map(cascade_node, 0);
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if (cascade_irq == NO_IRQ) {
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printk(KERN_ERR "Failed to map cascade interrupt\n");
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return;
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}
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DBG("mpc8544ds: cascade mapped to irq %d\n", cascade_irq);
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i8259_init(cascade_node, 0);
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of_node_put(cascade_node);
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set_irq_chained_handler(cascade_irq, mpc8544_8259_cascade);
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#endif /* CONFIG_PPC_I8259 */
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}
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#ifdef CONFIG_PCI
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enum pirq { PIRQA = 8, PIRQB, PIRQC, PIRQD, PIRQE, PIRQF, PIRQG, PIRQH };
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/*
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* Value in table -- IRQ number
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*/
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const unsigned char uli1575_irq_route_table[16] = {
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0, /* 0: Reserved */
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0x8,
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0, /* 2: Reserved */
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0x2,
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0x4,
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0x5,
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0x7,
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0x6,
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0, /* 8: Reserved */
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0x1,
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0x3,
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0x9,
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0xb,
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0, /* 13: Reserved */
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0xd,
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0xf,
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};
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static int __devinit
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get_pci_irq_from_of(struct pci_controller *hose, int slot, int pin)
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{
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struct of_irq oirq;
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u32 laddr[3];
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struct device_node *hosenode = hose ? hose->arch_data : NULL;
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if (!hosenode)
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return -EINVAL;
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laddr[0] = (hose->first_busno << 16) | (PCI_DEVFN(slot, 0) << 8);
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laddr[1] = laddr[2] = 0;
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of_irq_map_raw(hosenode, &pin, 1, laddr, &oirq);
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DBG("mpc8544_ds: pci irq addr %x, slot %d, pin %d, irq %d\n",
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laddr[0], slot, pin, oirq.specifier[0]);
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return oirq.specifier[0];
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}
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/*8259*/
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static void __devinit quirk_uli1575(struct pci_dev *dev)
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{
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unsigned short temp;
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struct pci_controller *hose = pci_bus_to_host(dev->bus);
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unsigned char irq2pin[16];
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unsigned long pirq_map_word = 0;
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u32 irq;
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int i;
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/*
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* ULI1575 interrupts route setup
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*/
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memset(irq2pin, 0, 16); /* Initialize default value 0 */
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irq2pin[6]=PIRQA+3; /* enabled mapping for IRQ6 to PIRQD, used by SATA */
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/*
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* PIRQE -> PIRQF mapping set manually
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*
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* IRQ pin IRQ#
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* PIRQE ---- 9
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* PIRQF ---- 10
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* PIRQG ---- 11
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* PIRQH ---- 12
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*/
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for (i = 0; i < 4; i++)
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irq2pin[i + 9] = PIRQE + i;
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/* Set IRQ-PIRQ Mapping to ULI1575 */
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for (i = 0; i < 16; i++)
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if (irq2pin[i])
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pirq_map_word |= (uli1575_irq_route_table[i] & 0xf)
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<< ((irq2pin[i] - PIRQA) * 4);
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pirq_map_word |= 1<<26; /* disable INTx in EP mode*/
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/* ULI1575 IRQ mapping conf register default value is 0xb9317542 */
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DBG("Setup ULI1575 IRQ mapping configuration register value = 0x%x\n",
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(int)pirq_map_word);
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pci_write_config_dword(dev, 0x48, pirq_map_word);
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#define ULI1575_SET_DEV_IRQ(slot, pin, reg) \
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do { \
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int irq; \
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irq = get_pci_irq_from_of(hose, slot, pin); \
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if (irq > 0 && irq < 16) \
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pci_write_config_byte(dev, reg, irq2pin[irq]); \
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else \
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printk(KERN_WARNING "ULI1575 device" \
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"(slot %d, pin %d) irq %d is invalid.\n", \
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slot, pin, irq); \
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} while(0)
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/* USB 1.1 OHCI controller 1, slot 28, pin 1 */
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ULI1575_SET_DEV_IRQ(28, 1, 0x86);
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/* USB 1.1 OHCI controller 2, slot 28, pin 2 */
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ULI1575_SET_DEV_IRQ(28, 2, 0x87);
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/* USB 1.1 OHCI controller 3, slot 28, pin 3 */
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ULI1575_SET_DEV_IRQ(28, 3, 0x88);
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/* USB 2.0 controller, slot 28, pin 4 */
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irq = get_pci_irq_from_of(hose, 28, 4);
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if (irq >= 0 && irq <= 15)
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pci_write_config_dword(dev, 0x74, uli1575_irq_route_table[irq]);
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/* Audio controller, slot 29, pin 1 */
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ULI1575_SET_DEV_IRQ(29, 1, 0x8a);
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/* Modem controller, slot 29, pin 2 */
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ULI1575_SET_DEV_IRQ(29, 2, 0x8b);
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/* HD audio controller, slot 29, pin 3 */
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ULI1575_SET_DEV_IRQ(29, 3, 0x8c);
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/* SMB interrupt: slot 30, pin 1 */
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ULI1575_SET_DEV_IRQ(30, 1, 0x8e);
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/* PMU ACPI SCI interrupt: slot 30, pin 2 */
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ULI1575_SET_DEV_IRQ(30, 2, 0x8f);
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/* Serial ATA interrupt: slot 31, pin 1 */
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ULI1575_SET_DEV_IRQ(31, 1, 0x8d);
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/* Primary PATA IDE IRQ: 14
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* Secondary PATA IDE IRQ: 15
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*/
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pci_write_config_byte(dev, 0x44, 0x30 | uli1575_irq_route_table[14]);
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pci_write_config_byte(dev, 0x75, uli1575_irq_route_table[15]);
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/* Set IRQ14 and IRQ15 to legacy IRQs */
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pci_read_config_word(dev, 0x46, &temp);
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temp |= 0xc000;
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pci_write_config_word(dev, 0x46, temp);
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/* Set i8259 interrupt trigger
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* IRQ 3: Level
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* IRQ 4: Level
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* IRQ 5: Level
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* IRQ 6: Level
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* IRQ 7: Level
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* IRQ 9: Level
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* IRQ 10: Level
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* IRQ 11: Level
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* IRQ 12: Level
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* IRQ 14: Edge
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* IRQ 15: Edge
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*/
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outb(0xfa, 0x4d0);
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outb(0x1e, 0x4d1);
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#undef ULI1575_SET_DEV_IRQ
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}
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/* SATA */
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static void __devinit quirk_uli5288(struct pci_dev *dev)
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{
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unsigned char c;
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pci_read_config_byte(dev, 0x83, &c);
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c |= 0x80; /* read/write lock */
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pci_write_config_byte(dev, 0x83, c);
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pci_write_config_byte(dev, 0x09, 0x01); /* Base class code: storage */
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pci_write_config_byte(dev, 0x0a, 0x06); /* IDE disk */
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pci_read_config_byte(dev, 0x83, &c);
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c &= 0x7f;
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pci_write_config_byte(dev, 0x83, c);
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pci_read_config_byte(dev, 0x84, &c);
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c |= 0x01; /* emulated PATA mode enabled */
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pci_write_config_byte(dev, 0x84, c);
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}
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/* PATA */
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static void __devinit quirk_uli5229(struct pci_dev *dev)
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{
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unsigned short temp;
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pci_write_config_word(dev, 0x04, 0x0405); /* MEM IO MSI */
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pci_read_config_word(dev, 0x4a, &temp);
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temp |= 0x1000; /* Enable Native IRQ 14/15 */
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pci_write_config_word(dev, 0x4a, temp);
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}
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/*Bridge*/
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static void __devinit early_uli5249(struct pci_dev *dev)
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{
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unsigned char temp;
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pci_write_config_word(dev, 0x04, 0x0007); /* mem access */
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pci_read_config_byte(dev, 0x7c, &temp);
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pci_write_config_byte(dev, 0x7c, 0x80); /* R/W lock control */
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pci_write_config_byte(dev, 0x09, 0x01); /* set as pci-pci bridge */
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pci_write_config_byte(dev, 0x7c, temp); /* restore pci bus debug control */
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dev->class |= 0x1;
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x1575, quirk_uli1575);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5288, quirk_uli5288);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5229, quirk_uli5229);
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AL, 0x5249, early_uli5249);
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#endif /* CONFIG_PCI */
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/*
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* Setup the architecture
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*/
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static void __init mpc8544_ds_setup_arch(void)
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{
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#ifdef CONFIG_PCI
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struct device_node *np;
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#endif
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if (ppc_md.progress)
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ppc_md.progress("mpc8544_ds_setup_arch()", 0);
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#ifdef CONFIG_PCI
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for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;) {
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struct resource rsrc;
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of_address_to_resource(np, 0, &rsrc);
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if ((rsrc.start & 0xfffff) == 0xb000)
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fsl_add_bridge(np, 1);
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else
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fsl_add_bridge(np, 0);
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}
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#endif
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printk("MPC8544 DS board from Freescale Semiconductor\n");
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}
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/*
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* Called very early, device-tree isn't unflattened
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*/
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static int __init mpc8544_ds_probe(void)
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{
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unsigned long root = of_get_flat_dt_root();
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return of_flat_dt_is_compatible(root, "MPC8544DS");
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}
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define_machine(mpc8544_ds) {
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.name = "MPC8544 DS",
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.probe = mpc8544_ds_probe,
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.setup_arch = mpc8544_ds_setup_arch,
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.init_IRQ = mpc8544_ds_pic_init,
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.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
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.get_irq = mpic_get_irq,
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.restart = mpc85xx_restart,
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.calibrate_decr = generic_calibrate_decr,
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.progress = udbg_progress,
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};
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