forked from Minki/linux
22dc132d54
A previous patch implemented an incomplete workaround of erratum
A-008171. The complete workaround is as below. This patch is to
implement the complete workaround which uses SW tuning if HW tuning
fails, and retries both HW/SW tuning once with reduced clock if
workaround fails. This is suggested by hardware team, and the patch
had been verified on LS1046A eSDHC + Phison 32G eMMC which could
trigger the erratum.
Workaround:
/* For T1040, T2080, LS1021A, T1023 Rev 1: */
1. Program TBPTR[TB_WNDW_END_PTR] = 3*DIV_RATIO.
2. Program TBPTR[TB_WNDW_START_PTR] = 5*DIV_RATIO.
3. Program the software tuning mode by setting TBCTL[TB_MODE] = 2'h3.
4. Set SYSCTL2[EXTN] and SYSCTL2[SAMPCLKSEL].
5. Issue SEND_TUNING_BLK Command (CMD19 for SD, CMD21 for MMC).
6. Wait for IRQSTAT[BRR], buffer read ready, to be set.
7. Clear IRQSTAT[BRR].
8. Check SYSCTL2[EXTN] to be cleared.
9. Check SYSCTL2[SAMPCLKSEL], Sampling Clock Select. It's set value
indicate tuning procedure success, and clear indicate failure.
In case of tuning failure, fixed sampling scheme could be used by
clearing TBCTL[TB_EN].
/* For LS1080A Rev 1, LS2088A Rev 1.0, LA1575A Rev 1.0: */
1. Read the TBCTL[31:0] register. Write TBCTL[11:8]=4'h8 and wait for
1ms.
2. Read the TBCTL[31:0] register and rewrite again. Wait for 1ms second.
3. Read the TBSTAT[31:0] register twice.
3.1 Reset data lines by setting ESDHCCTL[RSTD] bit.
3.2 Check ESDHCCTL[RSTD] bit.
3.3 If ESDHCCTL[RSTD] is 0, go to step 3.4 else go to step 3.2.
3.4 Write 32'hFFFF_FFFF to IRQSTAT register.
4. if TBSTAT[15:8]-TBSTAT[7:0] > 4*DIV_RATIO or TBSTAT[7:0]-TBSTAT[15:8]
> 4*DIV_RATIO , then program TBPTR[TB_WNDW_END_PTR] = 4*DIV_RATIO and
program TBPTR[TB_WNDW_START_PTR] = 8*DIV_RATIO.
/* For LS1012A Rev1, LS1043A Rev 1.x, LS1046A 1.0: */
1. Read the TBCTL[0:31] register. Write TBCTL[20:23]=4'h8 and wait for
1ms.
2. Read the TBCTL[0:31] register and rewrite again. Wait for 1ms second.
3. Read the TBSTAT[0:31] register twice.
3.1 Reset data lines by setting ESDHCCTL[RSTD] bit.
3.2 Check ESDHCCTL[RSTD] bit.
3.3 If ESDHCCTL[RSTD] is 0, go to step 3.4 else go to step 3.2.
3.4 Write 32'hFFFF_FFFF to IRQSTAT register.
4. if TBSTAT[16:23]-TBSTAT[24:31] > 4*DIV_RATIO or TBSTAT[24:31]-
TBSTAT[16:23] > 4* DIV_RATIO , then program TBPTR[TB_WNDW_END_PTR] =
4*DIV_RATIO and program TBPTR[TB_WNDW_START_PTR] = 8*DIV_RATIO.
/* For LS1080A Rev 1, LS2088A Rev 1.0, LA1575A Rev 1.0 LS1012A Rev1,
* LS1043A Rev 1.x, LS1046A 1.0:
*/
5. else program TBPTR[TB_WNDW_END_PTR] = 3*DIV_RATIO and program
TBPTR[TB_WNDW_START_PTR] = 5*DIV_RATIO.
6. Program the software tuning mode by setting TBCTL[TB_MODE] = 2'h3.
7. Set SYSCTL2[EXTN], wait 1us and SYSCTL2[SAMPCLKSEL].
8. Issue SEND_TUNING_BLK Command (CMD19 for SD, CMD21 for MMC).
9. Wait for IRQSTAT[BRR], buffer read ready, to be set.
10. Clear IRQSTAT[BRR].
11. Check SYSCTL2[EXTN] to be cleared.
12. Check SYSCTL2[SAMPCLKSEL], Sampling Clock Select. It's set value
indicate tuning procedure success, and clear indicate failure.
In case of tuning failure, fixed sampling scheme could be used by
clearing TBCTL[TB_EN].
Fixes: b1f378ab53 ("mmc: sdhci-of-esdhc: add erratum A008171 support")
Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
107 lines
2.9 KiB
C
107 lines
2.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
|
|
/*
|
|
* Freescale eSDHC controller driver generics for OF and pltfm.
|
|
*
|
|
* Copyright (c) 2007 Freescale Semiconductor, Inc.
|
|
* Copyright (c) 2009 MontaVista Software, Inc.
|
|
* Copyright (c) 2010 Pengutronix e.K.
|
|
* Author: Wolfram Sang <w.sang@pengutronix.de>
|
|
*/
|
|
|
|
#ifndef _DRIVERS_MMC_SDHCI_ESDHC_H
|
|
#define _DRIVERS_MMC_SDHCI_ESDHC_H
|
|
|
|
/*
|
|
* Ops and quirks for the Freescale eSDHC controller.
|
|
*/
|
|
|
|
#define ESDHC_DEFAULT_QUIRKS (SDHCI_QUIRK_FORCE_BLK_SZ_2048 | \
|
|
SDHCI_QUIRK_32BIT_DMA_ADDR | \
|
|
SDHCI_QUIRK_NO_BUSY_IRQ | \
|
|
SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | \
|
|
SDHCI_QUIRK_PIO_NEEDS_DELAY | \
|
|
SDHCI_QUIRK_NO_HISPD_BIT)
|
|
|
|
/* pltfm-specific */
|
|
#define ESDHC_HOST_CONTROL_LE 0x20
|
|
|
|
/*
|
|
* eSDHC register definition
|
|
*/
|
|
|
|
/* Present State Register */
|
|
#define ESDHC_PRSSTAT 0x24
|
|
#define ESDHC_CLOCK_STABLE 0x00000008
|
|
|
|
/* Protocol Control Register */
|
|
#define ESDHC_PROCTL 0x28
|
|
#define ESDHC_VOLT_SEL 0x00000400
|
|
#define ESDHC_CTRL_4BITBUS (0x1 << 1)
|
|
#define ESDHC_CTRL_8BITBUS (0x2 << 1)
|
|
#define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1)
|
|
#define ESDHC_HOST_CONTROL_RES 0x01
|
|
|
|
/* System Control Register */
|
|
#define ESDHC_SYSTEM_CONTROL 0x2c
|
|
#define ESDHC_CLOCK_MASK 0x0000fff0
|
|
#define ESDHC_PREDIV_SHIFT 8
|
|
#define ESDHC_DIVIDER_SHIFT 4
|
|
#define ESDHC_CLOCK_SDCLKEN 0x00000008
|
|
#define ESDHC_CLOCK_PEREN 0x00000004
|
|
#define ESDHC_CLOCK_HCKEN 0x00000002
|
|
#define ESDHC_CLOCK_IPGEN 0x00000001
|
|
|
|
/* System Control 2 Register */
|
|
#define ESDHC_SYSTEM_CONTROL_2 0x3c
|
|
#define ESDHC_SMPCLKSEL 0x00800000
|
|
#define ESDHC_EXTN 0x00400000
|
|
|
|
/* Host Controller Capabilities Register 2 */
|
|
#define ESDHC_CAPABILITIES_1 0x114
|
|
|
|
/* Tuning Block Control Register */
|
|
#define ESDHC_TBCTL 0x120
|
|
#define ESDHC_HS400_WNDW_ADJUST 0x00000040
|
|
#define ESDHC_HS400_MODE 0x00000010
|
|
#define ESDHC_TB_EN 0x00000004
|
|
#define ESDHC_TB_MODE_MASK 0x00000003
|
|
#define ESDHC_TB_MODE_SW 0x00000003
|
|
#define ESDHC_TB_MODE_3 0x00000002
|
|
|
|
#define ESDHC_TBSTAT 0x124
|
|
|
|
#define ESDHC_TBPTR 0x128
|
|
#define ESDHC_WNDW_STRT_PTR_SHIFT 8
|
|
#define ESDHC_WNDW_STRT_PTR_MASK (0x7f << 8)
|
|
#define ESDHC_WNDW_END_PTR_MASK 0x7f
|
|
|
|
/* SD Clock Control Register */
|
|
#define ESDHC_SDCLKCTL 0x144
|
|
#define ESDHC_LPBK_CLK_SEL 0x80000000
|
|
#define ESDHC_CMD_CLK_CTL 0x00008000
|
|
|
|
/* SD Timing Control Register */
|
|
#define ESDHC_SDTIMNGCTL 0x148
|
|
#define ESDHC_FLW_CTL_BG 0x00008000
|
|
|
|
/* DLL Config 0 Register */
|
|
#define ESDHC_DLLCFG0 0x160
|
|
#define ESDHC_DLL_ENABLE 0x80000000
|
|
#define ESDHC_DLL_FREQ_SEL 0x08000000
|
|
|
|
/* DLL Config 1 Register */
|
|
#define ESDHC_DLLCFG1 0x164
|
|
#define ESDHC_DLL_PD_PULSE_STRETCH_SEL 0x80000000
|
|
|
|
/* DLL Status 0 Register */
|
|
#define ESDHC_DLLSTAT0 0x170
|
|
#define ESDHC_DLL_STS_SLV_LOCK 0x08000000
|
|
|
|
/* Control Register for DMA transfer */
|
|
#define ESDHC_DMA_SYSCTL 0x40c
|
|
#define ESDHC_PERIPHERAL_CLK_SEL 0x00080000
|
|
#define ESDHC_FLUSH_ASYNC_FIFO 0x00040000
|
|
#define ESDHC_DMA_SNOOP 0x00000040
|
|
|
|
#endif /* _DRIVERS_MMC_SDHCI_ESDHC_H */
|