forked from Minki/linux
e21fd552ff
Display switch logic is added to notify the host side that
current vGPU have a valid surface to show. It does so by
writing the display_ready field in PV INFO page, and then
will be handled in the host side. This is useful to avoid
trickiness when the VM's framebuffer is being accessed in
the middle of VM modesetting, e.g. compositing the framebuffer
in the host side.
v2:
- move the notification code outside the 'else' in load sequence
- remove the notification code in intel_crtc_set_config()
v4:
- code rebase, no need to define another dev_priv
- use #define instead of enum for display readiness
Signed-off-by: Yu Zhang <yu.c.zhang@linux.intel.com>
Signed-off-by: Jike Song <jike.song@intel.com>
Signed-off-by: Zhiyuan Lv <zhiyuan.lv@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
92 lines
3.2 KiB
C
92 lines
3.2 KiB
C
/*
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* Copyright(c) 2011-2015 Intel Corporation. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifndef _I915_VGPU_H_
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#define _I915_VGPU_H_
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/* The MMIO offset of the shared info between guest and host emulator */
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#define VGT_PVINFO_PAGE 0x78000
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#define VGT_PVINFO_SIZE 0x1000
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/*
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* The following structure pages are defined in GEN MMIO space
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* for virtualization. (One page for now)
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*/
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#define VGT_MAGIC 0x4776544776544776 /* 'vGTvGTvG' */
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#define VGT_VERSION_MAJOR 1
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#define VGT_VERSION_MINOR 0
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#define INTEL_VGT_IF_VERSION_ENCODE(major, minor) ((major) << 16 | (minor))
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#define INTEL_VGT_IF_VERSION \
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INTEL_VGT_IF_VERSION_ENCODE(VGT_VERSION_MAJOR, VGT_VERSION_MINOR)
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struct vgt_if {
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uint64_t magic; /* VGT_MAGIC */
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uint16_t version_major;
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uint16_t version_minor;
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uint32_t vgt_id; /* ID of vGT instance */
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uint32_t rsv1[12]; /* pad to offset 0x40 */
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/*
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* Data structure to describe the balooning info of resources.
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* Each VM can only have one portion of continuous area for now.
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* (May support scattered resource in future)
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* (starting from offset 0x40)
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*/
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struct {
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/* Aperture register balooning */
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struct {
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uint32_t base;
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uint32_t size;
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} mappable_gmadr; /* aperture */
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/* GMADR register balooning */
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struct {
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uint32_t base;
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uint32_t size;
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} nonmappable_gmadr; /* non aperture */
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/* allowed fence registers */
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uint32_t fence_num;
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uint32_t rsv2[3];
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} avail_rs; /* available/assigned resource */
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uint32_t rsv3[0x200 - 24]; /* pad to half page */
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/*
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* The bottom half page is for response from Gfx driver to hypervisor.
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* Set to reserved fields temporarily by now.
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*/
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uint32_t rsv4;
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uint32_t display_ready; /* ready for display owner switch */
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uint32_t rsv5[0x200 - 2]; /* pad to one page */
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} __packed;
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#define vgtif_reg(x) \
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(VGT_PVINFO_PAGE + (long)&((struct vgt_if *)NULL)->x)
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/* vGPU display status to be used by the host side */
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#define VGT_DRV_DISPLAY_NOT_READY 0
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#define VGT_DRV_DISPLAY_READY 1 /* ready for display switch */
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extern void i915_check_vgpu(struct drm_device *dev);
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extern int intel_vgt_balloon(struct drm_device *dev);
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extern void intel_vgt_deballoon(void);
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#endif /* _I915_VGPU_H_ */
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