forked from Minki/linux
70bb62f8ec
RealView boards like PB11MPCore have 512MB of RAM available contiguously at 0x70000000. Half of the memory is mirrored at 0x00000000 for backwards compatibility. This patch adds the CONFIG_REALVIEW_HIGH_PHYS_OFFSET option option to change the physical base address so that the full amount of RAM is available to Linux. Note that the EB board has 256MB of RAM also mirrored at 0x70000000, the only board without this feature being PB1176. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
343 lines
10 KiB
C
343 lines
10 KiB
C
/*
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* linux/arch/arm/mach-realview/realview_pb11mp.c
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*
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* Copyright (C) 2008 ARM Limited
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* Copyright (C) 2000 Deep Blue Solutions Ltd
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/sysdev.h>
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#include <linux/amba/bus.h>
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#include <linux/io.h>
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#include <mach/hardware.h>
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#include <asm/irq.h>
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#include <asm/leds.h>
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#include <asm/mach-types.h>
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#include <asm/hardware/gic.h>
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#include <asm/hardware/icst307.h>
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#include <asm/hardware/cache-l2x0.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/flash.h>
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#include <asm/mach/map.h>
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#include <asm/mach/mmc.h>
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#include <asm/mach/time.h>
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#include <mach/board-pb11mp.h>
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#include <mach/irqs.h>
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#include "core.h"
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#include "clock.h"
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static struct map_desc realview_pb11mp_io_desc[] __initdata = {
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{
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.virtual = IO_ADDRESS(REALVIEW_SYS_BASE),
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.pfn = __phys_to_pfn(REALVIEW_SYS_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}, {
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.virtual = IO_ADDRESS(REALVIEW_PB11MP_GIC_CPU_BASE),
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.pfn = __phys_to_pfn(REALVIEW_PB11MP_GIC_CPU_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}, {
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.virtual = IO_ADDRESS(REALVIEW_PB11MP_GIC_DIST_BASE),
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.pfn = __phys_to_pfn(REALVIEW_PB11MP_GIC_DIST_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}, {
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.virtual = IO_ADDRESS(REALVIEW_TC11MP_GIC_CPU_BASE),
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.pfn = __phys_to_pfn(REALVIEW_TC11MP_GIC_CPU_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}, {
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.virtual = IO_ADDRESS(REALVIEW_TC11MP_GIC_DIST_BASE),
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.pfn = __phys_to_pfn(REALVIEW_TC11MP_GIC_DIST_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}, {
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.virtual = IO_ADDRESS(REALVIEW_SCTL_BASE),
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.pfn = __phys_to_pfn(REALVIEW_SCTL_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}, {
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.virtual = IO_ADDRESS(REALVIEW_PB11MP_TIMER0_1_BASE),
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.pfn = __phys_to_pfn(REALVIEW_PB11MP_TIMER0_1_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}, {
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.virtual = IO_ADDRESS(REALVIEW_PB11MP_TIMER2_3_BASE),
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.pfn = __phys_to_pfn(REALVIEW_PB11MP_TIMER2_3_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}, {
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.virtual = IO_ADDRESS(REALVIEW_TC11MP_L220_BASE),
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.pfn = __phys_to_pfn(REALVIEW_TC11MP_L220_BASE),
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.length = SZ_8K,
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.type = MT_DEVICE,
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},
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#ifdef CONFIG_DEBUG_LL
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{
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.virtual = IO_ADDRESS(REALVIEW_PB11MP_UART0_BASE),
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.pfn = __phys_to_pfn(REALVIEW_PB11MP_UART0_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE,
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},
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#endif
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};
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static void __init realview_pb11mp_map_io(void)
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{
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iotable_init(realview_pb11mp_io_desc, ARRAY_SIZE(realview_pb11mp_io_desc));
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}
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/*
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* RealView PB11MPCore AMBA devices
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*/
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#define GPIO2_IRQ { IRQ_PB11MP_GPIO2, NO_IRQ }
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#define GPIO2_DMA { 0, 0 }
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#define GPIO3_IRQ { IRQ_PB11MP_GPIO3, NO_IRQ }
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#define GPIO3_DMA { 0, 0 }
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#define AACI_IRQ { IRQ_TC11MP_AACI, NO_IRQ }
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#define AACI_DMA { 0x80, 0x81 }
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#define MMCI0_IRQ { IRQ_TC11MP_MMCI0A, IRQ_TC11MP_MMCI0B }
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#define MMCI0_DMA { 0x84, 0 }
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#define KMI0_IRQ { IRQ_TC11MP_KMI0, NO_IRQ }
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#define KMI0_DMA { 0, 0 }
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#define KMI1_IRQ { IRQ_TC11MP_KMI1, NO_IRQ }
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#define KMI1_DMA { 0, 0 }
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#define PB11MP_SMC_IRQ { NO_IRQ, NO_IRQ }
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#define PB11MP_SMC_DMA { 0, 0 }
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#define MPMC_IRQ { NO_IRQ, NO_IRQ }
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#define MPMC_DMA { 0, 0 }
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#define PB11MP_CLCD_IRQ { IRQ_PB11MP_CLCD, NO_IRQ }
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#define PB11MP_CLCD_DMA { 0, 0 }
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#define DMAC_IRQ { IRQ_PB11MP_DMAC, NO_IRQ }
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#define DMAC_DMA { 0, 0 }
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#define SCTL_IRQ { NO_IRQ, NO_IRQ }
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#define SCTL_DMA { 0, 0 }
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#define PB11MP_WATCHDOG_IRQ { IRQ_PB11MP_WATCHDOG, NO_IRQ }
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#define PB11MP_WATCHDOG_DMA { 0, 0 }
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#define PB11MP_GPIO0_IRQ { IRQ_PB11MP_GPIO0, NO_IRQ }
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#define PB11MP_GPIO0_DMA { 0, 0 }
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#define GPIO1_IRQ { IRQ_PB11MP_GPIO1, NO_IRQ }
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#define GPIO1_DMA { 0, 0 }
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#define PB11MP_RTC_IRQ { IRQ_TC11MP_RTC, NO_IRQ }
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#define PB11MP_RTC_DMA { 0, 0 }
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#define SCI_IRQ { IRQ_PB11MP_SCI, NO_IRQ }
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#define SCI_DMA { 7, 6 }
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#define PB11MP_UART0_IRQ { IRQ_TC11MP_UART0, NO_IRQ }
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#define PB11MP_UART0_DMA { 15, 14 }
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#define PB11MP_UART1_IRQ { IRQ_TC11MP_UART1, NO_IRQ }
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#define PB11MP_UART1_DMA { 13, 12 }
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#define PB11MP_UART2_IRQ { IRQ_PB11MP_UART2, NO_IRQ }
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#define PB11MP_UART2_DMA { 11, 10 }
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#define PB11MP_UART3_IRQ { IRQ_PB11MP_UART3, NO_IRQ }
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#define PB11MP_UART3_DMA { 0x86, 0x87 }
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#define PB11MP_SSP_IRQ { IRQ_PB11MP_SSP, NO_IRQ }
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#define PB11MP_SSP_DMA { 9, 8 }
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/* FPGA Primecells */
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AMBA_DEVICE(aaci, "fpga:04", AACI, NULL);
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AMBA_DEVICE(mmc0, "fpga:05", MMCI0, &realview_mmc0_plat_data);
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AMBA_DEVICE(kmi0, "fpga:06", KMI0, NULL);
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AMBA_DEVICE(kmi1, "fpga:07", KMI1, NULL);
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AMBA_DEVICE(uart3, "fpga:09", PB11MP_UART3, NULL);
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/* DevChip Primecells */
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AMBA_DEVICE(smc, "dev:00", PB11MP_SMC, NULL);
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AMBA_DEVICE(sctl, "dev:e0", SCTL, NULL);
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AMBA_DEVICE(wdog, "dev:e1", PB11MP_WATCHDOG, NULL);
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AMBA_DEVICE(gpio0, "dev:e4", PB11MP_GPIO0, NULL);
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AMBA_DEVICE(gpio1, "dev:e5", GPIO1, NULL);
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AMBA_DEVICE(gpio2, "dev:e6", GPIO2, NULL);
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AMBA_DEVICE(rtc, "dev:e8", PB11MP_RTC, NULL);
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AMBA_DEVICE(sci0, "dev:f0", SCI, NULL);
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AMBA_DEVICE(uart0, "dev:f1", PB11MP_UART0, NULL);
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AMBA_DEVICE(uart1, "dev:f2", PB11MP_UART1, NULL);
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AMBA_DEVICE(uart2, "dev:f3", PB11MP_UART2, NULL);
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AMBA_DEVICE(ssp0, "dev:f4", PB11MP_SSP, NULL);
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/* Primecells on the NEC ISSP chip */
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AMBA_DEVICE(clcd, "issp:20", PB11MP_CLCD, &clcd_plat_data);
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AMBA_DEVICE(dmac, "issp:30", DMAC, NULL);
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static struct amba_device *amba_devs[] __initdata = {
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&dmac_device,
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&uart0_device,
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&uart1_device,
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&uart2_device,
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&uart3_device,
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&smc_device,
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&clcd_device,
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&sctl_device,
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&wdog_device,
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&gpio0_device,
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&gpio1_device,
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&gpio2_device,
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&rtc_device,
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&sci0_device,
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&ssp0_device,
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&aaci_device,
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&mmc0_device,
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&kmi0_device,
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&kmi1_device,
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};
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/*
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* RealView PB11MPCore platform devices
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*/
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static struct resource realview_pb11mp_flash_resource[] = {
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[0] = {
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.start = REALVIEW_PB11MP_FLASH0_BASE,
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.end = REALVIEW_PB11MP_FLASH0_BASE + REALVIEW_PB11MP_FLASH0_SIZE - 1,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = REALVIEW_PB11MP_FLASH1_BASE,
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.end = REALVIEW_PB11MP_FLASH1_BASE + REALVIEW_PB11MP_FLASH1_SIZE - 1,
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.flags = IORESOURCE_MEM,
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},
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};
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static struct resource realview_pb11mp_smsc911x_resources[] = {
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[0] = {
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.start = REALVIEW_PB11MP_ETH_BASE,
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.end = REALVIEW_PB11MP_ETH_BASE + SZ_64K - 1,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = IRQ_TC11MP_ETH,
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.end = IRQ_TC11MP_ETH,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device realview_pb11mp_smsc911x_device = {
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.name = "smc911x",
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.id = 0,
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.num_resources = ARRAY_SIZE(realview_pb11mp_smsc911x_resources),
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.resource = realview_pb11mp_smsc911x_resources,
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};
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struct resource realview_pb11mp_cf_resources[] = {
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[0] = {
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.start = REALVIEW_PB11MP_CF_BASE,
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.end = REALVIEW_PB11MP_CF_BASE + SZ_4K - 1,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = REALVIEW_PB11MP_CF_MEM_BASE,
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.end = REALVIEW_PB11MP_CF_MEM_BASE + SZ_4K - 1,
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.flags = IORESOURCE_MEM,
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},
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[2] = {
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.start = -1, /* FIXME: Find correct irq */
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.end = -1,
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.flags = IORESOURCE_IRQ,
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},
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};
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struct platform_device realview_pb11mp_cf_device = {
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.name = "compactflash",
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.id = 0,
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.num_resources = ARRAY_SIZE(realview_pb11mp_cf_resources),
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.resource = realview_pb11mp_cf_resources,
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};
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static void __init gic_init_irq(void)
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{
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unsigned int pldctrl;
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/* new irq mode with no DCC */
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writel(0x0000a05f, __io_address(REALVIEW_SYS_LOCK));
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pldctrl = readl(__io_address(REALVIEW_SYS_BASE) + REALVIEW_PB11MP_SYS_PLD_CTRL1);
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pldctrl |= 2 << 22;
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writel(pldctrl, __io_address(REALVIEW_SYS_BASE) + REALVIEW_PB11MP_SYS_PLD_CTRL1);
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writel(0x00000000, __io_address(REALVIEW_SYS_LOCK));
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/* ARM11MPCore test chip GIC, primary */
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gic_cpu_base_addr = __io_address(REALVIEW_TC11MP_GIC_CPU_BASE);
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gic_dist_init(0, __io_address(REALVIEW_TC11MP_GIC_DIST_BASE), 29);
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gic_cpu_init(0, gic_cpu_base_addr);
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/* board GIC, secondary */
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gic_dist_init(1, __io_address(REALVIEW_PB11MP_GIC_DIST_BASE), IRQ_PB11MP_GIC_START);
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gic_cpu_init(1, __io_address(REALVIEW_PB11MP_GIC_CPU_BASE));
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gic_cascade_irq(1, IRQ_TC11MP_PB_IRQ1);
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}
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static void __init realview_pb11mp_timer_init(void)
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{
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timer0_va_base = __io_address(REALVIEW_PB11MP_TIMER0_1_BASE);
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timer1_va_base = __io_address(REALVIEW_PB11MP_TIMER0_1_BASE) + 0x20;
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timer2_va_base = __io_address(REALVIEW_PB11MP_TIMER2_3_BASE);
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timer3_va_base = __io_address(REALVIEW_PB11MP_TIMER2_3_BASE) + 0x20;
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#ifdef CONFIG_LOCAL_TIMERS
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twd_base_addr = __io_address(REALVIEW_TC11MP_TWD_BASE);
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twd_size = REALVIEW_TC11MP_TWD_SIZE;
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#endif
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realview_timer_init(IRQ_TC11MP_TIMER0_1);
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}
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static struct sys_timer realview_pb11mp_timer = {
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.init = realview_pb11mp_timer_init,
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};
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static void __init realview_pb11mp_init(void)
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{
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int i;
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#ifdef CONFIG_CACHE_L2X0
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/* 1MB (128KB/way), 8-way associativity, evmon/parity/share enabled
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* Bits: .... ...0 0111 1001 0000 .... .... .... */
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l2x0_init(__io_address(REALVIEW_TC11MP_L220_BASE), 0x00790000, 0xfe000fff);
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#endif
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clk_register(&realview_clcd_clk);
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realview_flash_register(realview_pb11mp_flash_resource,
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ARRAY_SIZE(realview_pb11mp_flash_resource));
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platform_device_register(&realview_pb11mp_smsc911x_device);
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platform_device_register(&realview_i2c_device);
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platform_device_register(&realview_pb11mp_cf_device);
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for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
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struct amba_device *d = amba_devs[i];
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amba_device_register(d, &iomem_resource);
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}
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#ifdef CONFIG_LEDS
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leds_event = realview_leds_event;
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#endif
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}
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MACHINE_START(REALVIEW_PB11MP, "ARM-RealView PB11MPCore")
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/* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
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.phys_io = REALVIEW_PB11MP_UART0_BASE,
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.io_pg_offst = (IO_ADDRESS(REALVIEW_PB11MP_UART0_BASE) >> 18) & 0xfffc,
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.boot_params = PHYS_OFFSET + 0x00000100,
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.map_io = realview_pb11mp_map_io,
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.init_irq = gic_init_irq,
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.timer = &realview_pb11mp_timer,
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.init_machine = realview_pb11mp_init,
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MACHINE_END
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