forked from Minki/linux
4a6369e993
This adds dpm support for rv6xx asics. This includes: - clockgating - dynamic engine clock scaling - dynamic memory clock scaling - dynamic voltage scaling - dynamic pcie gen1/gen2 switching Set radeon.dpm=1 to enable. v2: remove duplicate line v3: fix thermal interrupt check noticed by Jerome Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
724 lines
18 KiB
C
724 lines
18 KiB
C
/*
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* Copyright 2011 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Alex Deucher
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*/
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#include "drmP.h"
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#include "radeon.h"
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#include "r600d.h"
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#include "r600_dpm.h"
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#include "atom.h"
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const u32 r600_utc[R600_PM_NUMBER_OF_TC] =
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{
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R600_UTC_DFLT_00,
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R600_UTC_DFLT_01,
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R600_UTC_DFLT_02,
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R600_UTC_DFLT_03,
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R600_UTC_DFLT_04,
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R600_UTC_DFLT_05,
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R600_UTC_DFLT_06,
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R600_UTC_DFLT_07,
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R600_UTC_DFLT_08,
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R600_UTC_DFLT_09,
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R600_UTC_DFLT_10,
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R600_UTC_DFLT_11,
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R600_UTC_DFLT_12,
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R600_UTC_DFLT_13,
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R600_UTC_DFLT_14,
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};
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const u32 r600_dtc[R600_PM_NUMBER_OF_TC] =
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{
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R600_DTC_DFLT_00,
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R600_DTC_DFLT_01,
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R600_DTC_DFLT_02,
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R600_DTC_DFLT_03,
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R600_DTC_DFLT_04,
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R600_DTC_DFLT_05,
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R600_DTC_DFLT_06,
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R600_DTC_DFLT_07,
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R600_DTC_DFLT_08,
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R600_DTC_DFLT_09,
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R600_DTC_DFLT_10,
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R600_DTC_DFLT_11,
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R600_DTC_DFLT_12,
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R600_DTC_DFLT_13,
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R600_DTC_DFLT_14,
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};
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void r600_dpm_print_class_info(u32 class, u32 class2)
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{
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printk("\tui class: ");
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switch (class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
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case ATOM_PPLIB_CLASSIFICATION_UI_NONE:
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default:
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printk("none\n");
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break;
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case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
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printk("battery\n");
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break;
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case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
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printk("balanced\n");
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break;
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case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
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printk("performance\n");
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break;
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}
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printk("\tinternal class: ");
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if (((class & ~ATOM_PPLIB_CLASSIFICATION_UI_MASK) == 0) &&
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(class2 == 0))
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printk("none");
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else {
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if (class & ATOM_PPLIB_CLASSIFICATION_BOOT)
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printk("boot ");
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if (class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
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printk("thermal ");
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if (class & ATOM_PPLIB_CLASSIFICATION_LIMITEDPOWERSOURCE)
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printk("limited_pwr ");
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if (class & ATOM_PPLIB_CLASSIFICATION_REST)
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printk("rest ");
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if (class & ATOM_PPLIB_CLASSIFICATION_FORCED)
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printk("forced ");
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if (class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
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printk("3d_perf ");
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if (class & ATOM_PPLIB_CLASSIFICATION_OVERDRIVETEMPLATE)
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printk("ovrdrv ");
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if (class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
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printk("uvd ");
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if (class & ATOM_PPLIB_CLASSIFICATION_3DLOW)
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printk("3d_low ");
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if (class & ATOM_PPLIB_CLASSIFICATION_ACPI)
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printk("acpi ");
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if (class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
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printk("uvd_hd2 ");
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if (class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
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printk("uvd_hd ");
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if (class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
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printk("uvd_sd ");
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if (class2 & ATOM_PPLIB_CLASSIFICATION2_LIMITEDPOWERSOURCE_2)
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printk("limited_pwr2 ");
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if (class2 & ATOM_PPLIB_CLASSIFICATION2_ULV)
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printk("ulv ");
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if (class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
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printk("uvd_mvc ");
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}
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printk("\n");
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}
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void r600_dpm_print_cap_info(u32 caps)
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{
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printk("\tcaps: ");
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if (caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY)
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printk("single_disp ");
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if (caps & ATOM_PPLIB_SUPPORTS_VIDEO_PLAYBACK)
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printk("video ");
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if (caps & ATOM_PPLIB_DISALLOW_ON_DC)
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printk("no_dc ");
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printk("\n");
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}
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void r600_dpm_print_ps_status(struct radeon_device *rdev,
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struct radeon_ps *rps)
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{
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printk("\tstatus: ");
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if (rps == rdev->pm.dpm.current_ps)
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printk("c ");
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if (rps == rdev->pm.dpm.requested_ps)
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printk("r ");
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if (rps == rdev->pm.dpm.boot_ps)
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printk("b ");
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printk("\n");
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}
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void r600_calculate_u_and_p(u32 i, u32 r_c, u32 p_b,
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u32 *p, u32 *u)
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{
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u32 b_c = 0;
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u32 i_c;
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u32 tmp;
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i_c = (i * r_c) / 100;
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tmp = i_c >> p_b;
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while (tmp) {
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b_c++;
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tmp >>= 1;
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}
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*u = (b_c + 1) / 2;
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*p = i_c / (1 << (2 * (*u)));
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}
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int r600_calculate_at(u32 t, u32 h, u32 fh, u32 fl, u32 *tl, u32 *th)
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{
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u32 k, a, ah, al;
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u32 t1;
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if ((fl == 0) || (fh == 0) || (fl > fh))
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return -EINVAL;
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k = (100 * fh) / fl;
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t1 = (t * (k - 100));
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a = (1000 * (100 * h + t1)) / (10000 + (t1 / 100));
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a = (a + 5) / 10;
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ah = ((a * t) + 5000) / 10000;
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al = a - ah;
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*th = t - ah;
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*tl = t + al;
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return 0;
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}
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void r600_gfx_clockgating_enable(struct radeon_device *rdev, bool enable)
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{
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int i;
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if (enable) {
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WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN);
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} else {
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WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN);
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WREG32(CG_RLC_REQ_AND_RSP, 0x2);
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for (i = 0; i < rdev->usec_timeout; i++) {
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if (((RREG32(CG_RLC_REQ_AND_RSP) & CG_RLC_RSP_TYPE_MASK) >> CG_RLC_RSP_TYPE_SHIFT) == 1)
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break;
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udelay(1);
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}
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WREG32(CG_RLC_REQ_AND_RSP, 0x0);
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WREG32(GRBM_PWR_CNTL, 0x1);
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RREG32(GRBM_PWR_CNTL);
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}
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}
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void r600_dynamicpm_enable(struct radeon_device *rdev, bool enable)
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{
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if (enable)
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WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN);
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else
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WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN);
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}
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void r600_enable_thermal_protection(struct radeon_device *rdev, bool enable)
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{
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if (enable)
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WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
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else
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WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
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}
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void r600_enable_acpi_pm(struct radeon_device *rdev)
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{
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WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN);
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}
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void r600_enable_dynamic_pcie_gen2(struct radeon_device *rdev, bool enable)
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{
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if (enable)
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WREG32_P(GENERAL_PWRMGT, ENABLE_GEN2PCIE, ~ENABLE_GEN2PCIE);
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else
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WREG32_P(GENERAL_PWRMGT, 0, ~ENABLE_GEN2PCIE);
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}
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bool r600_dynamicpm_enabled(struct radeon_device *rdev)
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{
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if (RREG32(GENERAL_PWRMGT) & GLOBAL_PWRMGT_EN)
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return true;
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else
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return false;
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}
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void r600_enable_sclk_control(struct radeon_device *rdev, bool enable)
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{
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if (enable)
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WREG32_P(GENERAL_PWRMGT, 0, ~SCLK_PWRMGT_OFF);
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else
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WREG32_P(GENERAL_PWRMGT, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);
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}
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void r600_enable_mclk_control(struct radeon_device *rdev, bool enable)
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{
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if (enable)
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WREG32_P(MCLK_PWRMGT_CNTL, 0, ~MPLL_PWRMGT_OFF);
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else
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WREG32_P(MCLK_PWRMGT_CNTL, MPLL_PWRMGT_OFF, ~MPLL_PWRMGT_OFF);
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}
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void r600_enable_spll_bypass(struct radeon_device *rdev, bool enable)
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{
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if (enable)
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WREG32_P(CG_SPLL_FUNC_CNTL, SPLL_BYPASS_EN, ~SPLL_BYPASS_EN);
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else
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WREG32_P(CG_SPLL_FUNC_CNTL, 0, ~SPLL_BYPASS_EN);
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}
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void r600_wait_for_spll_change(struct radeon_device *rdev)
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{
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int i;
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for (i = 0; i < rdev->usec_timeout; i++) {
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if (RREG32(CG_SPLL_FUNC_CNTL) & SPLL_CHG_STATUS)
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break;
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udelay(1);
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}
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}
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void r600_set_bsp(struct radeon_device *rdev, u32 u, u32 p)
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{
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WREG32(CG_BSP, BSP(p) | BSU(u));
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}
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void r600_set_at(struct radeon_device *rdev,
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u32 l_to_m, u32 m_to_h,
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u32 h_to_m, u32 m_to_l)
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{
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WREG32(CG_RT, FLS(l_to_m) | FMS(m_to_h));
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WREG32(CG_LT, FHS(h_to_m) | FMS(m_to_l));
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}
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void r600_set_tc(struct radeon_device *rdev,
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u32 index, u32 u_t, u32 d_t)
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{
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WREG32(CG_FFCT_0 + (index * 4), UTC_0(u_t) | DTC_0(d_t));
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}
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void r600_select_td(struct radeon_device *rdev,
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enum r600_td td)
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{
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if (td == R600_TD_AUTO)
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WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL);
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else
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WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL);
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if (td == R600_TD_UP)
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WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE);
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if (td == R600_TD_DOWN)
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WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE);
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}
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void r600_set_vrc(struct radeon_device *rdev, u32 vrv)
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{
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WREG32(CG_FTV, vrv);
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}
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void r600_set_tpu(struct radeon_device *rdev, u32 u)
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{
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WREG32_P(CG_TPC, TPU(u), ~TPU_MASK);
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}
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void r600_set_tpc(struct radeon_device *rdev, u32 c)
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{
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WREG32_P(CG_TPC, TPCC(c), ~TPCC_MASK);
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}
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void r600_set_sstu(struct radeon_device *rdev, u32 u)
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{
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WREG32_P(CG_SSP, CG_SSTU(u), ~CG_SSTU_MASK);
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}
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void r600_set_sst(struct radeon_device *rdev, u32 t)
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{
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WREG32_P(CG_SSP, CG_SST(t), ~CG_SST_MASK);
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}
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void r600_set_git(struct radeon_device *rdev, u32 t)
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{
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WREG32_P(CG_GIT, CG_GICST(t), ~CG_GICST_MASK);
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}
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void r600_set_fctu(struct radeon_device *rdev, u32 u)
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{
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WREG32_P(CG_FC_T, FC_TU(u), ~FC_TU_MASK);
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}
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void r600_set_fct(struct radeon_device *rdev, u32 t)
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{
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WREG32_P(CG_FC_T, FC_T(t), ~FC_T_MASK);
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}
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void r600_set_ctxcgtt3d_rphc(struct radeon_device *rdev, u32 p)
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{
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WREG32_P(CG_CTX_CGTT3D_R, PHC(p), ~PHC_MASK);
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}
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void r600_set_ctxcgtt3d_rsdc(struct radeon_device *rdev, u32 s)
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{
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WREG32_P(CG_CTX_CGTT3D_R, SDC(s), ~SDC_MASK);
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}
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void r600_set_vddc3d_oorsu(struct radeon_device *rdev, u32 u)
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{
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WREG32_P(CG_VDDC3D_OOR, SU(u), ~SU_MASK);
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}
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void r600_set_vddc3d_oorphc(struct radeon_device *rdev, u32 p)
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{
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WREG32_P(CG_VDDC3D_OOR, PHC(p), ~PHC_MASK);
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}
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void r600_set_vddc3d_oorsdc(struct radeon_device *rdev, u32 s)
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{
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WREG32_P(CG_VDDC3D_OOR, SDC(s), ~SDC_MASK);
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}
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void r600_set_mpll_lock_time(struct radeon_device *rdev, u32 lock_time)
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{
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WREG32_P(MPLL_TIME, MPLL_LOCK_TIME(lock_time), ~MPLL_LOCK_TIME_MASK);
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}
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void r600_set_mpll_reset_time(struct radeon_device *rdev, u32 reset_time)
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{
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WREG32_P(MPLL_TIME, MPLL_RESET_TIME(reset_time), ~MPLL_RESET_TIME_MASK);
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}
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void r600_engine_clock_entry_enable(struct radeon_device *rdev,
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u32 index, bool enable)
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{
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if (enable)
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WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART2 + (index * 4 * 2),
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STEP_0_SPLL_ENTRY_VALID, ~STEP_0_SPLL_ENTRY_VALID);
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else
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WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART2 + (index * 4 * 2),
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0, ~STEP_0_SPLL_ENTRY_VALID);
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}
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void r600_engine_clock_entry_enable_pulse_skipping(struct radeon_device *rdev,
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u32 index, bool enable)
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{
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if (enable)
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WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART2 + (index * 4 * 2),
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STEP_0_SPLL_STEP_ENABLE, ~STEP_0_SPLL_STEP_ENABLE);
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else
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WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART2 + (index * 4 * 2),
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0, ~STEP_0_SPLL_STEP_ENABLE);
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}
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void r600_engine_clock_entry_enable_post_divider(struct radeon_device *rdev,
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u32 index, bool enable)
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{
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if (enable)
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WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART2 + (index * 4 * 2),
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STEP_0_POST_DIV_EN, ~STEP_0_POST_DIV_EN);
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else
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WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART2 + (index * 4 * 2),
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0, ~STEP_0_POST_DIV_EN);
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}
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void r600_engine_clock_entry_set_post_divider(struct radeon_device *rdev,
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u32 index, u32 divider)
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{
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WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART1 + (index * 4 * 2),
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STEP_0_SPLL_POST_DIV(divider), ~STEP_0_SPLL_POST_DIV_MASK);
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}
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void r600_engine_clock_entry_set_reference_divider(struct radeon_device *rdev,
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u32 index, u32 divider)
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{
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WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART1 + (index * 4 * 2),
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STEP_0_SPLL_REF_DIV(divider), ~STEP_0_SPLL_REF_DIV_MASK);
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}
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|
|
void r600_engine_clock_entry_set_feedback_divider(struct radeon_device *rdev,
|
|
u32 index, u32 divider)
|
|
{
|
|
WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART1 + (index * 4 * 2),
|
|
STEP_0_SPLL_FB_DIV(divider), ~STEP_0_SPLL_FB_DIV_MASK);
|
|
}
|
|
|
|
void r600_engine_clock_entry_set_step_time(struct radeon_device *rdev,
|
|
u32 index, u32 step_time)
|
|
{
|
|
WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART1 + (index * 4 * 2),
|
|
STEP_0_SPLL_STEP_TIME(step_time), ~STEP_0_SPLL_STEP_TIME_MASK);
|
|
}
|
|
|
|
void r600_vid_rt_set_ssu(struct radeon_device *rdev, u32 u)
|
|
{
|
|
WREG32_P(VID_RT, SSTU(u), ~SSTU_MASK);
|
|
}
|
|
|
|
void r600_vid_rt_set_vru(struct radeon_device *rdev, u32 u)
|
|
{
|
|
WREG32_P(VID_RT, VID_CRTU(u), ~VID_CRTU_MASK);
|
|
}
|
|
|
|
void r600_vid_rt_set_vrt(struct radeon_device *rdev, u32 rt)
|
|
{
|
|
WREG32_P(VID_RT, VID_CRT(rt), ~VID_CRT_MASK);
|
|
}
|
|
|
|
void r600_voltage_control_enable_pins(struct radeon_device *rdev,
|
|
u64 mask)
|
|
{
|
|
WREG32(LOWER_GPIO_ENABLE, mask & 0xffffffff);
|
|
WREG32(UPPER_GPIO_ENABLE, upper_32_bits(mask));
|
|
}
|
|
|
|
|
|
void r600_voltage_control_program_voltages(struct radeon_device *rdev,
|
|
enum r600_power_level index, u64 pins)
|
|
{
|
|
u32 tmp, mask;
|
|
u32 ix = 3 - (3 & index);
|
|
|
|
WREG32(CTXSW_VID_LOWER_GPIO_CNTL + (ix * 4), pins & 0xffffffff);
|
|
|
|
mask = 7 << (3 * ix);
|
|
tmp = RREG32(VID_UPPER_GPIO_CNTL);
|
|
tmp = (tmp & ~mask) | ((pins >> (32 - (3 * ix))) & mask);
|
|
WREG32(VID_UPPER_GPIO_CNTL, tmp);
|
|
}
|
|
|
|
void r600_voltage_control_deactivate_static_control(struct radeon_device *rdev,
|
|
u64 mask)
|
|
{
|
|
u32 gpio;
|
|
|
|
gpio = RREG32(GPIOPAD_MASK);
|
|
gpio &= ~mask;
|
|
WREG32(GPIOPAD_MASK, gpio);
|
|
|
|
gpio = RREG32(GPIOPAD_EN);
|
|
gpio &= ~mask;
|
|
WREG32(GPIOPAD_EN, gpio);
|
|
|
|
gpio = RREG32(GPIOPAD_A);
|
|
gpio &= ~mask;
|
|
WREG32(GPIOPAD_A, gpio);
|
|
}
|
|
|
|
void r600_power_level_enable(struct radeon_device *rdev,
|
|
enum r600_power_level index, bool enable)
|
|
{
|
|
u32 ix = 3 - (3 & index);
|
|
|
|
if (enable)
|
|
WREG32_P(CTXSW_PROFILE_INDEX + (ix * 4), CTXSW_FREQ_STATE_ENABLE,
|
|
~CTXSW_FREQ_STATE_ENABLE);
|
|
else
|
|
WREG32_P(CTXSW_PROFILE_INDEX + (ix * 4), 0,
|
|
~CTXSW_FREQ_STATE_ENABLE);
|
|
}
|
|
|
|
void r600_power_level_set_voltage_index(struct radeon_device *rdev,
|
|
enum r600_power_level index, u32 voltage_index)
|
|
{
|
|
u32 ix = 3 - (3 & index);
|
|
|
|
WREG32_P(CTXSW_PROFILE_INDEX + (ix * 4),
|
|
CTXSW_FREQ_VIDS_CFG_INDEX(voltage_index), ~CTXSW_FREQ_VIDS_CFG_INDEX_MASK);
|
|
}
|
|
|
|
void r600_power_level_set_mem_clock_index(struct radeon_device *rdev,
|
|
enum r600_power_level index, u32 mem_clock_index)
|
|
{
|
|
u32 ix = 3 - (3 & index);
|
|
|
|
WREG32_P(CTXSW_PROFILE_INDEX + (ix * 4),
|
|
CTXSW_FREQ_MCLK_CFG_INDEX(mem_clock_index), ~CTXSW_FREQ_MCLK_CFG_INDEX_MASK);
|
|
}
|
|
|
|
void r600_power_level_set_eng_clock_index(struct radeon_device *rdev,
|
|
enum r600_power_level index, u32 eng_clock_index)
|
|
{
|
|
u32 ix = 3 - (3 & index);
|
|
|
|
WREG32_P(CTXSW_PROFILE_INDEX + (ix * 4),
|
|
CTXSW_FREQ_SCLK_CFG_INDEX(eng_clock_index), ~CTXSW_FREQ_SCLK_CFG_INDEX_MASK);
|
|
}
|
|
|
|
void r600_power_level_set_watermark_id(struct radeon_device *rdev,
|
|
enum r600_power_level index,
|
|
enum r600_display_watermark watermark_id)
|
|
{
|
|
u32 ix = 3 - (3 & index);
|
|
u32 tmp = 0;
|
|
|
|
if (watermark_id == R600_DISPLAY_WATERMARK_HIGH)
|
|
tmp = CTXSW_FREQ_DISPLAY_WATERMARK;
|
|
WREG32_P(CTXSW_PROFILE_INDEX + (ix * 4), tmp, ~CTXSW_FREQ_DISPLAY_WATERMARK);
|
|
}
|
|
|
|
void r600_power_level_set_pcie_gen2(struct radeon_device *rdev,
|
|
enum r600_power_level index, bool compatible)
|
|
{
|
|
u32 ix = 3 - (3 & index);
|
|
u32 tmp = 0;
|
|
|
|
if (compatible)
|
|
tmp = CTXSW_FREQ_GEN2PCIE_VOLT;
|
|
WREG32_P(CTXSW_PROFILE_INDEX + (ix * 4), tmp, ~CTXSW_FREQ_GEN2PCIE_VOLT);
|
|
}
|
|
|
|
enum r600_power_level r600_power_level_get_current_index(struct radeon_device *rdev)
|
|
{
|
|
u32 tmp;
|
|
|
|
tmp = RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_PROFILE_INDEX_MASK;
|
|
tmp >>= CURRENT_PROFILE_INDEX_SHIFT;
|
|
return tmp;
|
|
}
|
|
|
|
enum r600_power_level r600_power_level_get_target_index(struct radeon_device *rdev)
|
|
{
|
|
u32 tmp;
|
|
|
|
tmp = RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & TARGET_PROFILE_INDEX_MASK;
|
|
tmp >>= TARGET_PROFILE_INDEX_SHIFT;
|
|
return tmp;
|
|
}
|
|
|
|
void r600_power_level_set_enter_index(struct radeon_device *rdev,
|
|
enum r600_power_level index)
|
|
{
|
|
WREG32_P(TARGET_AND_CURRENT_PROFILE_INDEX, DYN_PWR_ENTER_INDEX(index),
|
|
~DYN_PWR_ENTER_INDEX_MASK);
|
|
}
|
|
|
|
void r600_wait_for_power_level_unequal(struct radeon_device *rdev,
|
|
enum r600_power_level index)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < rdev->usec_timeout; i++) {
|
|
if (r600_power_level_get_target_index(rdev) != index)
|
|
break;
|
|
udelay(1);
|
|
}
|
|
|
|
for (i = 0; i < rdev->usec_timeout; i++) {
|
|
if (r600_power_level_get_current_index(rdev) != index)
|
|
break;
|
|
udelay(1);
|
|
}
|
|
}
|
|
|
|
void r600_wait_for_power_level(struct radeon_device *rdev,
|
|
enum r600_power_level index)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < rdev->usec_timeout; i++) {
|
|
if (r600_power_level_get_target_index(rdev) == index)
|
|
break;
|
|
udelay(1);
|
|
}
|
|
|
|
for (i = 0; i < rdev->usec_timeout; i++) {
|
|
if (r600_power_level_get_current_index(rdev) == index)
|
|
break;
|
|
udelay(1);
|
|
}
|
|
}
|
|
|
|
void r600_start_dpm(struct radeon_device *rdev)
|
|
{
|
|
r600_enable_sclk_control(rdev, false);
|
|
r600_enable_mclk_control(rdev, false);
|
|
|
|
r600_dynamicpm_enable(rdev, true);
|
|
|
|
radeon_wait_for_vblank(rdev, 0);
|
|
radeon_wait_for_vblank(rdev, 1);
|
|
|
|
r600_enable_spll_bypass(rdev, true);
|
|
r600_wait_for_spll_change(rdev);
|
|
r600_enable_spll_bypass(rdev, false);
|
|
r600_wait_for_spll_change(rdev);
|
|
|
|
r600_enable_spll_bypass(rdev, true);
|
|
r600_wait_for_spll_change(rdev);
|
|
r600_enable_spll_bypass(rdev, false);
|
|
r600_wait_for_spll_change(rdev);
|
|
|
|
r600_enable_sclk_control(rdev, true);
|
|
r600_enable_mclk_control(rdev, true);
|
|
}
|
|
|
|
void r600_stop_dpm(struct radeon_device *rdev)
|
|
{
|
|
r600_dynamicpm_enable(rdev, false);
|
|
}
|
|
|
|
bool r600_is_uvd_state(u32 class, u32 class2)
|
|
{
|
|
if (class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
|
|
return true;
|
|
if (class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
|
|
return true;
|
|
if (class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
|
|
return true;
|
|
if (class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
|
|
return true;
|
|
if (class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
|
|
return true;
|
|
return false;
|
|
}
|
|
|
|
int r600_set_thermal_temperature_range(struct radeon_device *rdev,
|
|
int min_temp, int max_temp)
|
|
{
|
|
int low_temp = 0 * 1000;
|
|
int high_temp = 255 * 1000;
|
|
|
|
if (low_temp < min_temp)
|
|
low_temp = min_temp;
|
|
if (high_temp > max_temp)
|
|
high_temp = max_temp;
|
|
if (high_temp < low_temp) {
|
|
DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
|
|
return -EINVAL;
|
|
}
|
|
|
|
WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK);
|
|
WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK);
|
|
WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK);
|
|
|
|
rdev->pm.dpm.thermal.min_temp = low_temp;
|
|
rdev->pm.dpm.thermal.max_temp = high_temp;
|
|
|
|
return 0;
|
|
}
|
|
|
|
bool r600_is_internal_thermal_sensor(enum radeon_int_thermal_type sensor)
|
|
{
|
|
switch (sensor) {
|
|
case THERMAL_TYPE_RV6XX:
|
|
case THERMAL_TYPE_RV770:
|
|
case THERMAL_TYPE_EVERGREEN:
|
|
case THERMAL_TYPE_SUMO:
|
|
case THERMAL_TYPE_NI:
|
|
return true;
|
|
case THERMAL_TYPE_ADT7473_WITH_INTERNAL:
|
|
case THERMAL_TYPE_EMC2103_WITH_INTERNAL:
|
|
return false; /* need special handling */
|
|
case THERMAL_TYPE_NONE:
|
|
case THERMAL_TYPE_EXTERNAL:
|
|
case THERMAL_TYPE_EXTERNAL_GPIO:
|
|
default:
|
|
return false;
|
|
}
|
|
}
|