6b1fb6f703
Instead of storing the concepts dictionary inside header file, move it to the subsystem documentation. Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
179 lines
6.1 KiB
ReStructuredText
179 lines
6.1 KiB
ReStructuredText
Error Detection And Correction (EDAC) Devices
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=============================================
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Main Concepts used at the EDAC subsystem
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----------------------------------------
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There are several things to be aware of that aren't at all obvious, like
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*sockets, *socket sets*, *banks*, *rows*, *chip-select rows*, *channels*,
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etc...
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These are some of the many terms that are thrown about that don't always
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mean what people think they mean (Inconceivable!). In the interest of
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creating a common ground for discussion, terms and their definitions
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will be established.
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* Memory devices
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The individual DRAM chips on a memory stick. These devices commonly
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output 4 and 8 bits each (x4, x8). Grouping several of these in parallel
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provides the number of bits that the memory controller expects:
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typically 72 bits, in order to provide 64 bits + 8 bits of ECC data.
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* Memory Stick
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A printed circuit board that aggregates multiple memory devices in
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parallel. In general, this is the Field Replaceable Unit (FRU) which
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gets replaced, in the case of excessive errors. Most often it is also
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called DIMM (Dual Inline Memory Module).
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* Memory Socket
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A physical connector on the motherboard that accepts a single memory
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stick. Also called as "slot" on several datasheets.
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* Channel
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A memory controller channel, responsible to communicate with a group of
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DIMMs. Each channel has its own independent control (command) and data
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bus, and can be used independently or grouped with other channels.
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* Branch
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It is typically the highest hierarchy on a Fully-Buffered DIMM memory
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controller. Typically, it contains two channels. Two channels at the
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same branch can be used in single mode or in lockstep mode. When
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lockstep is enabled, the cacheline is doubled, but it generally brings
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some performance penalty. Also, it is generally not possible to point to
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just one memory stick when an error occurs, as the error correction code
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is calculated using two DIMMs instead of one. Due to that, it is capable
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of correcting more errors than on single mode.
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* Single-channel
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The data accessed by the memory controller is contained into one dimm
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only. E. g. if the data is 64 bits-wide, the data flows to the CPU using
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one 64 bits parallel access. Typically used with SDR, DDR, DDR2 and DDR3
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memories. FB-DIMM and RAMBUS use a different concept for channel, so
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this concept doesn't apply there.
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* Double-channel
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The data size accessed by the memory controller is interlaced into two
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dimms, accessed at the same time. E. g. if the DIMM is 64 bits-wide (72
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bits with ECC), the data flows to the CPU using a 128 bits parallel
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access.
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* Chip-select row
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This is the name of the DRAM signal used to select the DRAM ranks to be
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accessed. Common chip-select rows for single channel are 64 bits, for
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dual channel 128 bits. It may not be visible by the memory controller,
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as some DIMM types have a memory buffer that can hide direct access to
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it from the Memory Controller.
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* Single-Ranked stick
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A Single-ranked stick has 1 chip-select row of memory. Motherboards
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commonly drive two chip-select pins to a memory stick. A single-ranked
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stick, will occupy only one of those rows. The other will be unused.
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.. _doubleranked:
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* Double-Ranked stick
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A double-ranked stick has two chip-select rows which access different
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sets of memory devices. The two rows cannot be accessed concurrently.
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* Double-sided stick
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**DEPRECATED TERM**, see :ref:`Double-Ranked stick <doubleranked>`.
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A double-sided stick has two chip-select rows which access different sets
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of memory devices. The two rows cannot be accessed concurrently.
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"Double-sided" is irrespective of the memory devices being mounted on
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both sides of the memory stick.
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* Socket set
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All of the memory sticks that are required for a single memory access or
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all of the memory sticks spanned by a chip-select row. A single socket
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set has two chip-select rows and if double-sided sticks are used these
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will occupy those chip-select rows.
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* Bank
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This term is avoided because it is unclear when needing to distinguish
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between chip-select rows and socket sets.
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Memory Controllers
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------------------
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Most of the EDAC core is focused on doing Memory Controller error detection.
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The :c:func:`edac_mc_alloc`. It uses internally the struct ``mem_ctl_info``
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to describe the memory controllers, with is an opaque struct for the EDAC
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drivers. Only the EDAC core is allowed to touch it.
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.. kernel-doc:: include/linux/edac.h
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.. kernel-doc:: drivers/edac/edac_mc.h
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PCI Controllers
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---------------
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The EDAC subsystem provides a mechanism to handle PCI controllers by calling
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the :c:func:`edac_pci_alloc_ctl_info`. It will use the struct
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:c:type:`edac_pci_ctl_info` to describe the PCI controllers.
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.. kernel-doc:: drivers/edac/edac_pci.h
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EDAC Blocks
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-----------
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The EDAC subsystem also provides a generic mechanism to report errors on
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other parts of the hardware via :c:func:`edac_device_alloc_ctl_info` function.
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The structures :c:type:`edac_dev_sysfs_block_attribute`,
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:c:type:`edac_device_block`, :c:type:`edac_device_instance` and
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:c:type:`edac_device_ctl_info` provide a generic or abstract 'edac_device'
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representation at sysfs.
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This set of structures and the code that implements the APIs for the same, provide for registering EDAC type devices which are NOT standard memory or
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PCI, like:
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- CPU caches (L1 and L2)
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- DMA engines
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- Core CPU switches
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- Fabric switch units
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- PCIe interface controllers
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- other EDAC/ECC type devices that can be monitored for
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errors, etc.
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It allows for a 2 level set of hierarchy.
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For example, a cache could be composed of L1, L2 and L3 levels of cache.
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Each CPU core would have its own L1 cache, while sharing L2 and maybe L3
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caches. On such case, those can be represented via the following sysfs
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nodes::
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/sys/devices/system/edac/..
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pci/ <existing pci directory (if available)>
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mc/ <existing memory device directory>
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cpu/cpu0/.. <L1 and L2 block directory>
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/L1-cache/ce_count
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/ue_count
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/L2-cache/ce_count
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/ue_count
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cpu/cpu1/.. <L1 and L2 block directory>
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/L1-cache/ce_count
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/ue_count
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/L2-cache/ce_count
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/ue_count
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...
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the L1 and L2 directories would be "edac_device_block's"
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.. kernel-doc:: drivers/edac/edac_device.h
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