____cacheline_aligned is an insufficient guarantee for non-coherent DMA on platforms with 128 byte cachelines above L1. Switch to the updated IIO_DMA_MINALIGN definition. Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Cc: Rodrigo Siqueira <rodrigosiqueiramelo@gmail.com> Link: https://lore.kernel.org/r/20220807151218.656881-4-jic23@kernel.org |
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accel | ||
adc | ||
addac | ||
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frequency | ||
impedance-analyzer | ||
meter | ||
resolver | ||
Kconfig | ||
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TODO |