forked from Minki/linux
ff9f29abf0
There are instances (such as non-recoverable GPU page faults) where NVKM decides that a channel's context is no longer viable, and will be removed from the runlist. This commit notifies the owner of the channel when this happens, so it has the opportunity to take some kind of recovery action instead of hanging. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
286 lines
8.0 KiB
C
286 lines
8.0 KiB
C
/*
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* Copyright 2012 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include "channv50.h"
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#include <core/client.h>
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#include <core/ramht.h>
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#include <subdev/mmu.h>
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#include <subdev/timer.h>
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#include <nvif/cl826e.h>
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static int
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g84_fifo_chan_ntfy(struct nvkm_fifo_chan *chan, u32 type,
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struct nvkm_event **pevent)
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{
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switch (type) {
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case NV826E_V0_NTFY_NON_STALL_INTERRUPT:
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*pevent = &chan->fifo->uevent;
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return 0;
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default:
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break;
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}
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return -EINVAL;
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}
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static int
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g84_fifo_chan_engine(struct nvkm_engine *engine)
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{
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switch (engine->subdev.index) {
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case NVKM_ENGINE_GR : return 0;
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case NVKM_ENGINE_MPEG :
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case NVKM_ENGINE_MSPPP : return 1;
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case NVKM_ENGINE_CE0 : return 2;
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case NVKM_ENGINE_VP :
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case NVKM_ENGINE_MSPDEC: return 3;
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case NVKM_ENGINE_CIPHER:
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case NVKM_ENGINE_SEC : return 4;
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case NVKM_ENGINE_BSP :
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case NVKM_ENGINE_MSVLD : return 5;
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default:
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WARN_ON(1);
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return 0;
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}
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}
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static int
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g84_fifo_chan_engine_addr(struct nvkm_engine *engine)
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{
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switch (engine->subdev.index) {
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case NVKM_ENGINE_DMAOBJ:
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case NVKM_ENGINE_SW : return -1;
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case NVKM_ENGINE_GR : return 0x0020;
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case NVKM_ENGINE_VP :
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case NVKM_ENGINE_MSPDEC: return 0x0040;
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case NVKM_ENGINE_MPEG :
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case NVKM_ENGINE_MSPPP : return 0x0060;
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case NVKM_ENGINE_BSP :
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case NVKM_ENGINE_MSVLD : return 0x0080;
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case NVKM_ENGINE_CIPHER:
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case NVKM_ENGINE_SEC : return 0x00a0;
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case NVKM_ENGINE_CE0 : return 0x00c0;
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default:
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WARN_ON(1);
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return -1;
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}
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}
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static int
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g84_fifo_chan_engine_fini(struct nvkm_fifo_chan *base,
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struct nvkm_engine *engine, bool suspend)
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{
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struct nv50_fifo_chan *chan = nv50_fifo_chan(base);
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struct nv50_fifo *fifo = chan->fifo;
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struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
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struct nvkm_device *device = subdev->device;
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u32 engn, save;
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int offset;
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bool done;
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offset = g84_fifo_chan_engine_addr(engine);
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if (offset < 0)
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return 0;
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engn = g84_fifo_chan_engine(engine);
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save = nvkm_mask(device, 0x002520, 0x0000003f, 1 << engn);
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nvkm_wr32(device, 0x0032fc, chan->base.inst->addr >> 12);
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done = nvkm_msec(device, 2000,
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if (nvkm_rd32(device, 0x0032fc) != 0xffffffff)
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break;
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) >= 0;
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nvkm_wr32(device, 0x002520, save);
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if (!done) {
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nvkm_error(subdev, "channel %d [%s] unload timeout\n",
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chan->base.chid, chan->base.object.client->name);
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if (suspend)
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return -EBUSY;
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}
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nvkm_kmap(chan->eng);
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nvkm_wo32(chan->eng, offset + 0x00, 0x00000000);
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nvkm_wo32(chan->eng, offset + 0x04, 0x00000000);
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nvkm_wo32(chan->eng, offset + 0x08, 0x00000000);
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nvkm_wo32(chan->eng, offset + 0x0c, 0x00000000);
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nvkm_wo32(chan->eng, offset + 0x10, 0x00000000);
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nvkm_wo32(chan->eng, offset + 0x14, 0x00000000);
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nvkm_done(chan->eng);
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return 0;
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}
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static int
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g84_fifo_chan_engine_init(struct nvkm_fifo_chan *base,
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struct nvkm_engine *engine)
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{
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struct nv50_fifo_chan *chan = nv50_fifo_chan(base);
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struct nvkm_gpuobj *engn = chan->engn[engine->subdev.index];
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u64 limit, start;
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int offset;
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offset = g84_fifo_chan_engine_addr(engine);
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if (offset < 0)
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return 0;
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limit = engn->addr + engn->size - 1;
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start = engn->addr;
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nvkm_kmap(chan->eng);
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nvkm_wo32(chan->eng, offset + 0x00, 0x00190000);
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nvkm_wo32(chan->eng, offset + 0x04, lower_32_bits(limit));
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nvkm_wo32(chan->eng, offset + 0x08, lower_32_bits(start));
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nvkm_wo32(chan->eng, offset + 0x0c, upper_32_bits(limit) << 24 |
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upper_32_bits(start));
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nvkm_wo32(chan->eng, offset + 0x10, 0x00000000);
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nvkm_wo32(chan->eng, offset + 0x14, 0x00000000);
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nvkm_done(chan->eng);
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return 0;
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}
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static int
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g84_fifo_chan_engine_ctor(struct nvkm_fifo_chan *base,
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struct nvkm_engine *engine,
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struct nvkm_object *object)
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{
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struct nv50_fifo_chan *chan = nv50_fifo_chan(base);
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int engn = engine->subdev.index;
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if (g84_fifo_chan_engine_addr(engine) < 0)
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return 0;
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return nvkm_object_bind(object, NULL, 0, &chan->engn[engn]);
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}
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static int
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g84_fifo_chan_object_ctor(struct nvkm_fifo_chan *base,
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struct nvkm_object *object)
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{
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struct nv50_fifo_chan *chan = nv50_fifo_chan(base);
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u32 handle = object->handle;
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u32 context;
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switch (object->engine->subdev.index) {
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case NVKM_ENGINE_DMAOBJ:
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case NVKM_ENGINE_SW : context = 0x00000000; break;
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case NVKM_ENGINE_GR : context = 0x00100000; break;
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case NVKM_ENGINE_MPEG :
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case NVKM_ENGINE_MSPPP : context = 0x00200000; break;
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case NVKM_ENGINE_ME :
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case NVKM_ENGINE_CE0 : context = 0x00300000; break;
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case NVKM_ENGINE_VP :
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case NVKM_ENGINE_MSPDEC: context = 0x00400000; break;
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case NVKM_ENGINE_CIPHER:
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case NVKM_ENGINE_SEC :
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case NVKM_ENGINE_VIC : context = 0x00500000; break;
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case NVKM_ENGINE_BSP :
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case NVKM_ENGINE_MSVLD : context = 0x00600000; break;
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default:
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WARN_ON(1);
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return -EINVAL;
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}
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return nvkm_ramht_insert(chan->ramht, object, 0, 4, handle, context);
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}
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static void
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g84_fifo_chan_init(struct nvkm_fifo_chan *base)
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{
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struct nv50_fifo_chan *chan = nv50_fifo_chan(base);
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struct nv50_fifo *fifo = chan->fifo;
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struct nvkm_device *device = fifo->base.engine.subdev.device;
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u64 addr = chan->ramfc->addr >> 8;
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u32 chid = chan->base.chid;
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nvkm_wr32(device, 0x002600 + (chid * 4), 0x80000000 | addr);
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nv50_fifo_runlist_update(fifo);
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}
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static const struct nvkm_fifo_chan_func
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g84_fifo_chan_func = {
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.dtor = nv50_fifo_chan_dtor,
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.init = g84_fifo_chan_init,
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.fini = nv50_fifo_chan_fini,
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.ntfy = g84_fifo_chan_ntfy,
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.engine_ctor = g84_fifo_chan_engine_ctor,
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.engine_dtor = nv50_fifo_chan_engine_dtor,
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.engine_init = g84_fifo_chan_engine_init,
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.engine_fini = g84_fifo_chan_engine_fini,
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.object_ctor = g84_fifo_chan_object_ctor,
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.object_dtor = nv50_fifo_chan_object_dtor,
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};
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int
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g84_fifo_chan_ctor(struct nv50_fifo *fifo, u64 vm, u64 push,
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const struct nvkm_oclass *oclass,
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struct nv50_fifo_chan *chan)
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{
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struct nvkm_device *device = fifo->base.engine.subdev.device;
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int ret;
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ret = nvkm_fifo_chan_ctor(&g84_fifo_chan_func, &fifo->base,
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0x10000, 0x1000, false, vm, push,
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(1ULL << NVKM_ENGINE_BSP) |
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(1ULL << NVKM_ENGINE_CE0) |
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(1ULL << NVKM_ENGINE_CIPHER) |
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(1ULL << NVKM_ENGINE_DMAOBJ) |
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(1ULL << NVKM_ENGINE_GR) |
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(1ULL << NVKM_ENGINE_ME) |
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(1ULL << NVKM_ENGINE_MPEG) |
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(1ULL << NVKM_ENGINE_MSPDEC) |
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(1ULL << NVKM_ENGINE_MSPPP) |
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(1ULL << NVKM_ENGINE_MSVLD) |
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(1ULL << NVKM_ENGINE_SEC) |
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(1ULL << NVKM_ENGINE_SW) |
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(1ULL << NVKM_ENGINE_VIC) |
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(1ULL << NVKM_ENGINE_VP),
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0, 0xc00000, 0x2000, oclass, &chan->base);
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chan->fifo = fifo;
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if (ret)
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return ret;
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ret = nvkm_gpuobj_new(device, 0x0200, 0, true, chan->base.inst,
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&chan->eng);
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if (ret)
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return ret;
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ret = nvkm_gpuobj_new(device, 0x4000, 0, false, chan->base.inst,
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&chan->pgd);
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if (ret)
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return ret;
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ret = nvkm_gpuobj_new(device, 0x1000, 0x400, true, chan->base.inst,
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&chan->cache);
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if (ret)
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return ret;
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ret = nvkm_gpuobj_new(device, 0x100, 0x100, true, chan->base.inst,
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&chan->ramfc);
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if (ret)
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return ret;
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ret = nvkm_ramht_new(device, 0x8000, 16, chan->base.inst, &chan->ramht);
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if (ret)
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return ret;
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return nvkm_vm_ref(chan->base.vm, &chan->vm, chan->pgd);
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}
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