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linux/drivers/phy/cadence
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Swapnil Jakhade e25c9dbcfc phy: cadence-torrent: Update PCIe + QSGMII config for correct PLL1 clock 
For PCIe + QSGMII configuration where QSGMII was using PLL1 and was
expecting 10GHz clock, configuration was giving 8GHz clock. Update
register sequences to get correct PLL1 configuration.

Also, update single link PCIe and single link SGMII/QSGMII configurations
with related changes.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Link: https://lore.kernel.org/r/1614838096-32291-2-git-send-email-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-30 23:34:13 +05:30
..
cdns-dphy.c phy: cadence: convert to devm_platform_ioremap_resource 2020-11-16 12:47:46 +05:30
Kconfig phy: cadence-torrent: Add support to drive refclk out 2021-03-30 23:33:40 +05:30
Makefile phy: cadence: salvo: add salvo phy driver 2020-05-07 09:46:36 +05:30
phy-cadence-salvo.c phy: cadence: convert to devm_platform_ioremap_resource 2020-11-16 12:47:46 +05:30
phy-cadence-sierra.c phy: cadence: convert to devm_platform_ioremap_resource 2020-11-16 12:47:46 +05:30
phy-cadence-torrent.c phy: cadence-torrent: Update PCIe + QSGMII config for correct PLL1 clock 2021-03-30 23:34:13 +05:30