forked from Minki/linux
1306c08a7c
In order to handle errata I688, a page of sram was reserved by doing a static iotable map. Now that we use gen_pool to manage sram, we can completely remove all of these static mappings and use gen_pool_alloc() to get the one page of sram space needed to implement errata I688. omap_bus_sync will be NOP until SRAM initialization happens. Suggested-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
39 lines
715 B
Plaintext
39 lines
715 B
Plaintext
* TI - MPU (Main Processor Unit) subsystem
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The MPU subsystem contain one or several ARM cores
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depending of the version.
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The MPU contain CPUs, GIC, L2 cache and a local PRCM.
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Required properties:
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- compatible : Should be "ti,omap3-mpu" for OMAP3
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Should be "ti,omap4-mpu" for OMAP4
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Should be "ti,omap5-mpu" for OMAP5
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- ti,hwmods: "mpu"
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Optional properties:
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- sram: Phandle to the ocmcram node
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Examples:
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- For an OMAP5 SMP system:
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mpu {
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compatible = "ti,omap5-mpu";
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ti,hwmods = "mpu"
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};
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- For an OMAP4 SMP system:
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mpu {
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compatible = "ti,omap4-mpu";
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ti,hwmods = "mpu";
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};
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- For an OMAP3 monocore system:
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mpu {
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compatible = "ti,omap3-mpu";
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ti,hwmods = "mpu";
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};
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