forked from Minki/linux
4789d728e5
Make printings from IRQ appears in dmesg in chronological order Signed-off-by: Vladimir Kondratiev <qca_vkondrat@qca.qualcomm.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
492 lines
12 KiB
C
492 lines
12 KiB
C
/*
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* Copyright (c) 2012 Qualcomm Atheros, Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#include <linux/interrupt.h>
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#include "wil6210.h"
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/**
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* Theory of operation:
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*
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* There is ISR pseudo-cause register,
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* dma_rgf->DMA_RGF.PSEUDO_CAUSE.PSEUDO_CAUSE
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* Its bits represents OR'ed bits from 3 real ISR registers:
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* TX, RX, and MISC.
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*
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* Registers may be configured to either "write 1 to clear" or
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* "clear on read" mode
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*
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* When handling interrupt, one have to mask/unmask interrupts for the
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* real ISR registers, or hardware may malfunction.
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*
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*/
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#define WIL6210_IRQ_DISABLE (0xFFFFFFFFUL)
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#define WIL6210_IMC_RX BIT_DMA_EP_RX_ICR_RX_DONE
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#define WIL6210_IMC_TX (BIT_DMA_EP_TX_ICR_TX_DONE | \
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BIT_DMA_EP_TX_ICR_TX_DONE_N(0))
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#define WIL6210_IMC_MISC (ISR_MISC_FW_READY | \
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ISR_MISC_MBOX_EVT | \
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ISR_MISC_FW_ERROR)
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#define WIL6210_IRQ_PSEUDO_MASK (u32)(~(BIT_DMA_PSEUDO_CAUSE_RX | \
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BIT_DMA_PSEUDO_CAUSE_TX | \
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BIT_DMA_PSEUDO_CAUSE_MISC))
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#if defined(CONFIG_WIL6210_ISR_COR)
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/* configure to Clear-On-Read mode */
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#define WIL_ICR_ICC_VALUE (0xFFFFFFFFUL)
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static inline void wil_icr_clear(u32 x, void __iomem *addr)
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{
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}
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#else /* defined(CONFIG_WIL6210_ISR_COR) */
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/* configure to Write-1-to-Clear mode */
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#define WIL_ICR_ICC_VALUE (0UL)
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static inline void wil_icr_clear(u32 x, void __iomem *addr)
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{
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iowrite32(x, addr);
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}
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#endif /* defined(CONFIG_WIL6210_ISR_COR) */
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static inline u32 wil_ioread32_and_clear(void __iomem *addr)
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{
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u32 x = ioread32(addr);
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wil_icr_clear(x, addr);
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return x;
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}
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static void wil6210_mask_irq_tx(struct wil6210_priv *wil)
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{
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iowrite32(WIL6210_IRQ_DISABLE, wil->csr +
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HOSTADDR(RGF_DMA_EP_TX_ICR) +
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offsetof(struct RGF_ICR, IMS));
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}
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static void wil6210_mask_irq_rx(struct wil6210_priv *wil)
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{
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iowrite32(WIL6210_IRQ_DISABLE, wil->csr +
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HOSTADDR(RGF_DMA_EP_RX_ICR) +
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offsetof(struct RGF_ICR, IMS));
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}
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static void wil6210_mask_irq_misc(struct wil6210_priv *wil)
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{
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iowrite32(WIL6210_IRQ_DISABLE, wil->csr +
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HOSTADDR(RGF_DMA_EP_MISC_ICR) +
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offsetof(struct RGF_ICR, IMS));
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}
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static void wil6210_mask_irq_pseudo(struct wil6210_priv *wil)
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{
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wil_dbg_IRQ(wil, "%s()\n", __func__);
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iowrite32(WIL6210_IRQ_DISABLE, wil->csr +
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HOSTADDR(RGF_DMA_PSEUDO_CAUSE_MASK_SW));
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clear_bit(wil_status_irqen, &wil->status);
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}
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static void wil6210_unmask_irq_tx(struct wil6210_priv *wil)
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{
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iowrite32(WIL6210_IMC_TX, wil->csr +
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HOSTADDR(RGF_DMA_EP_TX_ICR) +
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offsetof(struct RGF_ICR, IMC));
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}
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static void wil6210_unmask_irq_rx(struct wil6210_priv *wil)
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{
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iowrite32(WIL6210_IMC_RX, wil->csr +
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HOSTADDR(RGF_DMA_EP_RX_ICR) +
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offsetof(struct RGF_ICR, IMC));
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}
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static void wil6210_unmask_irq_misc(struct wil6210_priv *wil)
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{
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iowrite32(WIL6210_IMC_MISC, wil->csr +
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HOSTADDR(RGF_DMA_EP_MISC_ICR) +
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offsetof(struct RGF_ICR, IMC));
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}
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static void wil6210_unmask_irq_pseudo(struct wil6210_priv *wil)
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{
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wil_dbg_IRQ(wil, "%s()\n", __func__);
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set_bit(wil_status_irqen, &wil->status);
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iowrite32(WIL6210_IRQ_PSEUDO_MASK, wil->csr +
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HOSTADDR(RGF_DMA_PSEUDO_CAUSE_MASK_SW));
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}
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void wil6210_disable_irq(struct wil6210_priv *wil)
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{
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wil_dbg_IRQ(wil, "%s()\n", __func__);
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wil6210_mask_irq_tx(wil);
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wil6210_mask_irq_rx(wil);
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wil6210_mask_irq_misc(wil);
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wil6210_mask_irq_pseudo(wil);
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}
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void wil6210_enable_irq(struct wil6210_priv *wil)
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{
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wil_dbg_IRQ(wil, "%s()\n", __func__);
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iowrite32(WIL_ICR_ICC_VALUE, wil->csr + HOSTADDR(RGF_DMA_EP_RX_ICR) +
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offsetof(struct RGF_ICR, ICC));
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iowrite32(WIL_ICR_ICC_VALUE, wil->csr + HOSTADDR(RGF_DMA_EP_TX_ICR) +
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offsetof(struct RGF_ICR, ICC));
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iowrite32(WIL_ICR_ICC_VALUE, wil->csr + HOSTADDR(RGF_DMA_EP_MISC_ICR) +
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offsetof(struct RGF_ICR, ICC));
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wil6210_unmask_irq_pseudo(wil);
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wil6210_unmask_irq_tx(wil);
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wil6210_unmask_irq_rx(wil);
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wil6210_unmask_irq_misc(wil);
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}
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static irqreturn_t wil6210_irq_rx(int irq, void *cookie)
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{
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struct wil6210_priv *wil = cookie;
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u32 isr = wil_ioread32_and_clear(wil->csr +
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HOSTADDR(RGF_DMA_EP_RX_ICR) +
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offsetof(struct RGF_ICR, ICR));
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wil_dbg_IRQ(wil, "ISR RX 0x%08x\n", isr);
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if (!isr) {
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wil_err(wil, "spurious IRQ: RX\n");
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return IRQ_NONE;
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}
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wil6210_mask_irq_rx(wil);
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if (isr & BIT_DMA_EP_RX_ICR_RX_DONE) {
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wil_dbg_IRQ(wil, "RX done\n");
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isr &= ~BIT_DMA_EP_RX_ICR_RX_DONE;
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wil_rx_handle(wil);
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}
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if (isr)
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wil_err(wil, "un-handled RX ISR bits 0x%08x\n", isr);
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wil6210_unmask_irq_rx(wil);
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return IRQ_HANDLED;
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}
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static irqreturn_t wil6210_irq_tx(int irq, void *cookie)
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{
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struct wil6210_priv *wil = cookie;
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u32 isr = wil_ioread32_and_clear(wil->csr +
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HOSTADDR(RGF_DMA_EP_TX_ICR) +
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offsetof(struct RGF_ICR, ICR));
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wil_dbg_IRQ(wil, "ISR TX 0x%08x\n", isr);
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if (!isr) {
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wil_err(wil, "spurious IRQ: TX\n");
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return IRQ_NONE;
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}
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wil6210_mask_irq_tx(wil);
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if (isr & BIT_DMA_EP_TX_ICR_TX_DONE) {
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uint i;
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wil_dbg_IRQ(wil, "TX done\n");
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isr &= ~BIT_DMA_EP_TX_ICR_TX_DONE;
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for (i = 0; i < 24; i++) {
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u32 mask = BIT_DMA_EP_TX_ICR_TX_DONE_N(i);
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if (isr & mask) {
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isr &= ~mask;
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wil_dbg_IRQ(wil, "TX done(%i)\n", i);
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wil_tx_complete(wil, i);
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}
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}
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}
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if (isr)
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wil_err(wil, "un-handled TX ISR bits 0x%08x\n", isr);
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wil6210_unmask_irq_tx(wil);
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return IRQ_HANDLED;
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}
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static void wil_notify_fw_error(struct wil6210_priv *wil)
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{
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struct device *dev = &wil_to_ndev(wil)->dev;
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char *envp[3] = {
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[0] = "SOURCE=wil6210",
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[1] = "EVENT=FW_ERROR",
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[2] = NULL,
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};
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kobject_uevent_env(&dev->kobj, KOBJ_CHANGE, envp);
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}
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static irqreturn_t wil6210_irq_misc(int irq, void *cookie)
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{
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struct wil6210_priv *wil = cookie;
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u32 isr = wil_ioread32_and_clear(wil->csr +
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HOSTADDR(RGF_DMA_EP_MISC_ICR) +
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offsetof(struct RGF_ICR, ICR));
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wil_dbg_IRQ(wil, "ISR MISC 0x%08x\n", isr);
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if (!isr) {
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wil_err(wil, "spurious IRQ: MISC\n");
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return IRQ_NONE;
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}
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wil6210_mask_irq_misc(wil);
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if (isr & ISR_MISC_FW_ERROR) {
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wil_dbg_IRQ(wil, "IRQ: Firmware error\n");
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clear_bit(wil_status_fwready, &wil->status);
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wil_notify_fw_error(wil);
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isr &= ~ISR_MISC_FW_ERROR;
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}
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if (isr & ISR_MISC_FW_READY) {
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wil_dbg_IRQ(wil, "IRQ: FW ready\n");
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/**
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* Actual FW ready indicated by the
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* WMI_FW_READY_EVENTID
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*/
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isr &= ~ISR_MISC_FW_READY;
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}
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wil->isr_misc = isr;
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if (isr) {
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return IRQ_WAKE_THREAD;
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} else {
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wil6210_unmask_irq_misc(wil);
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return IRQ_HANDLED;
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}
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}
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static irqreturn_t wil6210_irq_misc_thread(int irq, void *cookie)
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{
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struct wil6210_priv *wil = cookie;
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u32 isr = wil->isr_misc;
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wil_dbg_IRQ(wil, "Thread ISR MISC 0x%08x\n", isr);
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if (isr & ISR_MISC_MBOX_EVT) {
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wil_dbg_IRQ(wil, "MBOX event\n");
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wmi_recv_cmd(wil);
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isr &= ~ISR_MISC_MBOX_EVT;
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}
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if (isr)
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wil_err(wil, "un-handled MISC ISR bits 0x%08x\n", isr);
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wil->isr_misc = 0;
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wil6210_unmask_irq_misc(wil);
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return IRQ_HANDLED;
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}
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/**
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* thread IRQ handler
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*/
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static irqreturn_t wil6210_thread_irq(int irq, void *cookie)
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{
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struct wil6210_priv *wil = cookie;
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wil_dbg_IRQ(wil, "Thread IRQ\n");
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/* Discover real IRQ cause */
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if (wil->isr_misc)
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wil6210_irq_misc_thread(irq, cookie);
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wil6210_unmask_irq_pseudo(wil);
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return IRQ_HANDLED;
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}
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/* DEBUG
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* There is subtle bug in hardware that causes IRQ to raise when it should be
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* masked. It is quite rare and hard to debug.
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*
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* Catch irq issue if it happens and print all I can.
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*/
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static int wil6210_debug_irq_mask(struct wil6210_priv *wil, u32 pseudo_cause)
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{
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if (!test_bit(wil_status_irqen, &wil->status)) {
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u32 icm_rx = wil_ioread32_and_clear(wil->csr +
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HOSTADDR(RGF_DMA_EP_RX_ICR) +
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offsetof(struct RGF_ICR, ICM));
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u32 icr_rx = wil_ioread32_and_clear(wil->csr +
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HOSTADDR(RGF_DMA_EP_RX_ICR) +
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offsetof(struct RGF_ICR, ICR));
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u32 imv_rx = ioread32(wil->csr +
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HOSTADDR(RGF_DMA_EP_RX_ICR) +
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offsetof(struct RGF_ICR, IMV));
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u32 icm_tx = wil_ioread32_and_clear(wil->csr +
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HOSTADDR(RGF_DMA_EP_TX_ICR) +
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offsetof(struct RGF_ICR, ICM));
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u32 icr_tx = wil_ioread32_and_clear(wil->csr +
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HOSTADDR(RGF_DMA_EP_TX_ICR) +
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offsetof(struct RGF_ICR, ICR));
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u32 imv_tx = ioread32(wil->csr +
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HOSTADDR(RGF_DMA_EP_TX_ICR) +
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offsetof(struct RGF_ICR, IMV));
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u32 icm_misc = wil_ioread32_and_clear(wil->csr +
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HOSTADDR(RGF_DMA_EP_MISC_ICR) +
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offsetof(struct RGF_ICR, ICM));
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u32 icr_misc = wil_ioread32_and_clear(wil->csr +
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HOSTADDR(RGF_DMA_EP_MISC_ICR) +
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offsetof(struct RGF_ICR, ICR));
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u32 imv_misc = ioread32(wil->csr +
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HOSTADDR(RGF_DMA_EP_MISC_ICR) +
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offsetof(struct RGF_ICR, IMV));
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wil_err(wil, "IRQ when it should be masked: pseudo 0x%08x\n"
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"Rx icm:icr:imv 0x%08x 0x%08x 0x%08x\n"
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"Tx icm:icr:imv 0x%08x 0x%08x 0x%08x\n"
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"Misc icm:icr:imv 0x%08x 0x%08x 0x%08x\n",
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pseudo_cause,
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icm_rx, icr_rx, imv_rx,
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icm_tx, icr_tx, imv_tx,
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icm_misc, icr_misc, imv_misc);
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return -EINVAL;
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}
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return 0;
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}
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static irqreturn_t wil6210_hardirq(int irq, void *cookie)
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{
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irqreturn_t rc = IRQ_HANDLED;
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struct wil6210_priv *wil = cookie;
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u32 pseudo_cause = ioread32(wil->csr + HOSTADDR(RGF_DMA_PSEUDO_CAUSE));
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/**
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* pseudo_cause is Clear-On-Read, no need to ACK
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*/
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if ((pseudo_cause == 0) || ((pseudo_cause & 0xff) == 0xff))
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return IRQ_NONE;
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/* FIXME: IRQ mask debug */
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if (wil6210_debug_irq_mask(wil, pseudo_cause))
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return IRQ_NONE;
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wil_dbg_IRQ(wil, "Pseudo IRQ 0x%08x\n", pseudo_cause);
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wil6210_mask_irq_pseudo(wil);
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/* Discover real IRQ cause
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* There are 2 possible phases for every IRQ:
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* - hard IRQ handler called right here
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* - threaded handler called later
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*
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* Hard IRQ handler reads and clears ISR.
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*
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* If threaded handler requested, hard IRQ handler
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* returns IRQ_WAKE_THREAD and saves ISR register value
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* for the threaded handler use.
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*
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* voting for wake thread - need at least 1 vote
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*/
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if ((pseudo_cause & BIT_DMA_PSEUDO_CAUSE_RX) &&
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(wil6210_irq_rx(irq, cookie) == IRQ_WAKE_THREAD))
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rc = IRQ_WAKE_THREAD;
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if ((pseudo_cause & BIT_DMA_PSEUDO_CAUSE_TX) &&
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(wil6210_irq_tx(irq, cookie) == IRQ_WAKE_THREAD))
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rc = IRQ_WAKE_THREAD;
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if ((pseudo_cause & BIT_DMA_PSEUDO_CAUSE_MISC) &&
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(wil6210_irq_misc(irq, cookie) == IRQ_WAKE_THREAD))
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rc = IRQ_WAKE_THREAD;
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/* if thread is requested, it will unmask IRQ */
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if (rc != IRQ_WAKE_THREAD)
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wil6210_unmask_irq_pseudo(wil);
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return rc;
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}
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static int wil6210_request_3msi(struct wil6210_priv *wil, int irq)
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{
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int rc;
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/*
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* IRQ's are in the following order:
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* - Tx
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* - Rx
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* - Misc
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*/
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rc = request_irq(irq, wil6210_irq_tx, IRQF_SHARED,
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WIL_NAME"_tx", wil);
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if (rc)
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return rc;
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rc = request_irq(irq + 1, wil6210_irq_rx, IRQF_SHARED,
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WIL_NAME"_rx", wil);
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if (rc)
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goto free0;
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rc = request_threaded_irq(irq + 2, wil6210_irq_misc,
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wil6210_irq_misc_thread,
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IRQF_SHARED, WIL_NAME"_misc", wil);
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if (rc)
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goto free1;
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return 0;
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/* error branch */
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free1:
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free_irq(irq + 1, wil);
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free0:
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free_irq(irq, wil);
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return rc;
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}
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int wil6210_init_irq(struct wil6210_priv *wil, int irq)
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{
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int rc;
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if (wil->n_msi == 3)
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rc = wil6210_request_3msi(wil, irq);
|
|
else
|
|
rc = request_threaded_irq(irq, wil6210_hardirq,
|
|
wil6210_thread_irq,
|
|
wil->n_msi ? 0 : IRQF_SHARED,
|
|
WIL_NAME, wil);
|
|
if (rc)
|
|
return rc;
|
|
|
|
wil6210_enable_irq(wil);
|
|
|
|
return 0;
|
|
}
|
|
|
|
void wil6210_fini_irq(struct wil6210_priv *wil, int irq)
|
|
{
|
|
wil6210_disable_irq(wil);
|
|
free_irq(irq, wil);
|
|
if (wil->n_msi == 3) {
|
|
free_irq(irq + 1, wil);
|
|
free_irq(irq + 2, wil);
|
|
}
|
|
}
|