forked from Minki/linux
dc1a8bc16c
Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license v2 as published by the free software foundation this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not see http www gnu org licenses extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 2 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190531190111.856624369@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
231 lines
5.4 KiB
C
231 lines
5.4 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Zynq PLL driver
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*
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* Copyright (C) 2013 Xilinx
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*
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* Sören Brinkmann <soren.brinkmann@xilinx.com>
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*/
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#include <linux/clk/zynq.h>
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#include <linux/clk-provider.h>
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#include <linux/slab.h>
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#include <linux/io.h>
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/**
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* struct zynq_pll
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* @hw: Handle between common and hardware-specific interfaces
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* @pll_ctrl: PLL control register
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* @pll_status: PLL status register
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* @lock: Register lock
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* @lockbit: Indicates the associated PLL_LOCKED bit in the PLL status
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* register.
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*/
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struct zynq_pll {
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struct clk_hw hw;
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void __iomem *pll_ctrl;
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void __iomem *pll_status;
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spinlock_t *lock;
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u8 lockbit;
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};
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#define to_zynq_pll(_hw) container_of(_hw, struct zynq_pll, hw)
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/* Register bitfield defines */
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#define PLLCTRL_FBDIV_MASK 0x7f000
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#define PLLCTRL_FBDIV_SHIFT 12
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#define PLLCTRL_BPQUAL_MASK (1 << 3)
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#define PLLCTRL_PWRDWN_MASK 2
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#define PLLCTRL_PWRDWN_SHIFT 1
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#define PLLCTRL_RESET_MASK 1
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#define PLLCTRL_RESET_SHIFT 0
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#define PLL_FBDIV_MIN 13
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#define PLL_FBDIV_MAX 66
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/**
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* zynq_pll_round_rate() - Round a clock frequency
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* @hw: Handle between common and hardware-specific interfaces
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* @rate: Desired clock frequency
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* @prate: Clock frequency of parent clock
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* Returns frequency closest to @rate the hardware can generate.
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*/
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static long zynq_pll_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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u32 fbdiv;
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fbdiv = DIV_ROUND_CLOSEST(rate, *prate);
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if (fbdiv < PLL_FBDIV_MIN)
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fbdiv = PLL_FBDIV_MIN;
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else if (fbdiv > PLL_FBDIV_MAX)
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fbdiv = PLL_FBDIV_MAX;
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return *prate * fbdiv;
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}
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/**
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* zynq_pll_recalc_rate() - Recalculate clock frequency
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* @hw: Handle between common and hardware-specific interfaces
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* @parent_rate: Clock frequency of parent clock
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* Returns current clock frequency.
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*/
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static unsigned long zynq_pll_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct zynq_pll *clk = to_zynq_pll(hw);
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u32 fbdiv;
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/*
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* makes probably sense to redundantly save fbdiv in the struct
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* zynq_pll to save the IO access.
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*/
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fbdiv = (readl(clk->pll_ctrl) & PLLCTRL_FBDIV_MASK) >>
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PLLCTRL_FBDIV_SHIFT;
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return parent_rate * fbdiv;
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}
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/**
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* zynq_pll_is_enabled - Check if a clock is enabled
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* @hw: Handle between common and hardware-specific interfaces
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* Returns 1 if the clock is enabled, 0 otherwise.
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*
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* Not sure this is a good idea, but since disabled means bypassed for
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* this clock implementation we say we are always enabled.
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*/
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static int zynq_pll_is_enabled(struct clk_hw *hw)
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{
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unsigned long flags = 0;
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u32 reg;
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struct zynq_pll *clk = to_zynq_pll(hw);
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spin_lock_irqsave(clk->lock, flags);
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reg = readl(clk->pll_ctrl);
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spin_unlock_irqrestore(clk->lock, flags);
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return !(reg & (PLLCTRL_RESET_MASK | PLLCTRL_PWRDWN_MASK));
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}
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/**
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* zynq_pll_enable - Enable clock
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* @hw: Handle between common and hardware-specific interfaces
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* Returns 0 on success
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*/
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static int zynq_pll_enable(struct clk_hw *hw)
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{
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unsigned long flags = 0;
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u32 reg;
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struct zynq_pll *clk = to_zynq_pll(hw);
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if (zynq_pll_is_enabled(hw))
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return 0;
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pr_info("PLL: enable\n");
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/* Power up PLL and wait for lock */
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spin_lock_irqsave(clk->lock, flags);
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reg = readl(clk->pll_ctrl);
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reg &= ~(PLLCTRL_RESET_MASK | PLLCTRL_PWRDWN_MASK);
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writel(reg, clk->pll_ctrl);
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while (!(readl(clk->pll_status) & (1 << clk->lockbit)))
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;
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spin_unlock_irqrestore(clk->lock, flags);
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return 0;
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}
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/**
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* zynq_pll_disable - Disable clock
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* @hw: Handle between common and hardware-specific interfaces
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* Returns 0 on success
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*/
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static void zynq_pll_disable(struct clk_hw *hw)
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{
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unsigned long flags = 0;
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u32 reg;
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struct zynq_pll *clk = to_zynq_pll(hw);
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if (!zynq_pll_is_enabled(hw))
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return;
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pr_info("PLL: shutdown\n");
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/* shut down PLL */
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spin_lock_irqsave(clk->lock, flags);
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reg = readl(clk->pll_ctrl);
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reg |= PLLCTRL_RESET_MASK | PLLCTRL_PWRDWN_MASK;
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writel(reg, clk->pll_ctrl);
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spin_unlock_irqrestore(clk->lock, flags);
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}
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static const struct clk_ops zynq_pll_ops = {
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.enable = zynq_pll_enable,
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.disable = zynq_pll_disable,
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.is_enabled = zynq_pll_is_enabled,
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.round_rate = zynq_pll_round_rate,
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.recalc_rate = zynq_pll_recalc_rate
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};
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/**
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* clk_register_zynq_pll() - Register PLL with the clock framework
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* @name PLL name
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* @parent Parent clock name
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* @pll_ctrl Pointer to PLL control register
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* @pll_status Pointer to PLL status register
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* @lock_index Bit index to this PLL's lock status bit in @pll_status
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* @lock Register lock
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* Returns handle to the registered clock.
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*/
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struct clk *clk_register_zynq_pll(const char *name, const char *parent,
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void __iomem *pll_ctrl, void __iomem *pll_status, u8 lock_index,
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spinlock_t *lock)
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{
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struct zynq_pll *pll;
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struct clk *clk;
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u32 reg;
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const char *parent_arr[1] = {parent};
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unsigned long flags = 0;
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struct clk_init_data initd = {
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.name = name,
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.parent_names = parent_arr,
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.ops = &zynq_pll_ops,
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.num_parents = 1,
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.flags = 0
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};
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pll = kmalloc(sizeof(*pll), GFP_KERNEL);
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if (!pll)
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return ERR_PTR(-ENOMEM);
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/* Populate the struct */
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pll->hw.init = &initd;
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pll->pll_ctrl = pll_ctrl;
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pll->pll_status = pll_status;
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pll->lockbit = lock_index;
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pll->lock = lock;
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spin_lock_irqsave(pll->lock, flags);
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reg = readl(pll->pll_ctrl);
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reg &= ~PLLCTRL_BPQUAL_MASK;
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writel(reg, pll->pll_ctrl);
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spin_unlock_irqrestore(pll->lock, flags);
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clk = clk_register(NULL, &pll->hw);
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if (WARN_ON(IS_ERR(clk)))
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goto free_pll;
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return clk;
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free_pll:
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kfree(pll);
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return clk;
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}
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