forked from Minki/linux
6f630784cc
function that isn't used anymore. Otherwise the main new thing for the common clk framework is that it is selectable in the Kconfig language now. Hopefully this will let clk drivers and clk consumers be testable on more than the architectures that support the clk framework. The goal is to introduce some Kunit tests for the framework. Outside of the core framework we have the usual set of various driver updates and non-critical fixes. The dirstat shows that the new Baikal-T1 driver is the largest addition this time around in terms of lines of code. After that the x86 (Intel), Qualcomm, and Mediatek drivers introduce many lines to support new or upcoming SoCs. After that the dirstat shows the usual suspects working on their SoC support by fixing minor bugs, correcting data and converting some of their DT bindings to YAML. Core: - Allow the COMMON_CLK config to be selectable New Drivers: - Clk driver for Baikal-T1 SoCs - Mediatek MT6765 clock support - Support for Intel Agilex clks - Add support for X1830 and X1000 Ingenic SoC clk controllers - Add support for the new Renesas RZ/G1H (R8A7742) SoC - Add support for Qualcomm's MSM8939 Generic Clock Controller Updates: - Support IDT VersaClock 5P49V5925 - Bunch of updates for HSDK clock generation unit (CGU) driver - Start making audio and GPU clks work on Marvell MMP2/MMP3 SoCs - Add some GPU, NPU, and UFS clks to Qualcomm SM8150 driver - Enable supply regulators for GPU gdscs on Qualcomm SoCs - Add support for Si5342, Si5344 and Si5345 chips - Support custom flags in Xilinx zynq firmware - Various small fixes to the Xilinx clk driver - A single minor rounding fix for the legacy Allwinner clock support - A few patches from Abel Vesa as preparation of adding audiomix clock support on i.MX - A couple of cleanups from Anson Huang for i.MX clk-sscg-pll and clk-pllv3 drivers - Drop dependency on ARM64 for i.MX8M clock driver, to support aarch32 mode on aarch64 hardware - A series from Peng Fan to improve i.MX8M clock drivers, using composite clock for core and bus clk slice - Set a better parent clock for flexcan on i.MX6UL to support CiA102 defined bit rates - A couple changes for EMC frequency scaling on Tegra210 - Support for CPU frequency scaling on Tegra20/Tegra30 - New clk gate for CSI test pattern generator on Tegra210 - Regression fixes for Samsung exynos542x and exynos5433 SoCs - Use of fallthrough; attribute for Samsung s3c24xx - Updates and fixup HDMI and video clocks on Meson8b - Fixup reset polarity on Meson8b - Fix GPU glitch free mux switch on Meson gx and g12 - A minor fix for the currently unused suspend/resume handling on Renesas RZ/A1 and RZ/A2 - Two more conversions of Renesas DT bindings to json-schema - Add support for the USB 2.0 clock selector on Renesas R-Car M3-W+ -----BEGIN PGP SIGNATURE----- iQJFBAABCAAvFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAl7gEUgRHHNib3lkQGtl cm5lbC5vcmcACgkQrQKIl8bklSUemxAAlQKzx0yMS3yx5twJ4RSFUvf3hf4OqyPp O46soqADk+l69Z4SUUBsMjt8el5Sqmm4d1j1Gpfmgp3ZlumHCQK+qGYp48IXbwRP Jlo5sKNlNL6yhCd+ixPn4j7W/HbpGs4cciWOXkGQtYEGjhHm3Wllhd9MqpL2YjLx gZW60NqWtOe1XeB4ILyYQGisNwAGDi5XuBeNvxG12H/LaGC1mwtBX9yoNAehr9bF peJ2XnO02zFo73OCyzIOkw1uY4u7ZtwPdHGhymoGeVlcBWO6KwKesNkHnji/Grlv wMbsGLoRV/i3PL3q5kZIDigo8sqZ9RUG+9piRAoiLM5AgkSypw3/q9T+ujTfZp8t kgvFha6bLZz31UFmr4lBJPTT5Q/hAoe1W6RB6HZkx7XNqUpsAS04SwkQztAqkJqZ 9zlYJrXgLlP5qcNllJ6zvUWkMqtmIKW4ZkjYe4u84yk5Co7bX8DCYa+QOKCz+pV4 IbjRT62OrX2ZlXJYwkLb4m1nhZ7tBzhzIRP1umL0ukhxdomK6ofSNPzbBF9+t1eR /ai2/Ch6L6WIwDINEp+chO67/dJaj5W3WNqGMCmVt37myW1kBjH3eg0YG4cp7NYZ /jSjdWczQy/8BgY5V1009MRXI4uyazQxBw+apDcIGezamOKBmuwjBcvkf1D0mL2x Y6OclK5ljsw= =nuG5 -----END PGP SIGNATURE----- Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "This time around we have four lines of diff in the core framework, removing a function that isn't used anymore. Otherwise the main new thing for the common clk framework is that it is selectable in the Kconfig language now. Hopefully this will let clk drivers and clk consumers be testable on more than the architectures that support the clk framework. The goal is to introduce some Kunit tests for the framework. Outside of the core framework we have the usual set of various driver updates and non-critical fixes. The dirstat shows that the new Baikal-T1 driver is the largest addition this time around in terms of lines of code. After that the x86 (Intel), Qualcomm, and Mediatek drivers introduce many lines to support new or upcoming SoCs. After that the dirstat shows the usual suspects working on their SoC support by fixing minor bugs, correcting data and converting some of their DT bindings to YAML. Core: - Allow the COMMON_CLK config to be selectable New Drivers: - Clk driver for Baikal-T1 SoCs - Mediatek MT6765 clock support - Support for Intel Agilex clks - Add support for X1830 and X1000 Ingenic SoC clk controllers - Add support for the new Renesas RZ/G1H (R8A7742) SoC - Add support for Qualcomm's MSM8939 Generic Clock Controller Updates: - Support IDT VersaClock 5P49V5925 - Bunch of updates for HSDK clock generation unit (CGU) driver - Start making audio and GPU clks work on Marvell MMP2/MMP3 SoCs - Add some GPU, NPU, and UFS clks to Qualcomm SM8150 driver - Enable supply regulators for GPU gdscs on Qualcomm SoCs - Add support for Si5342, Si5344 and Si5345 chips - Support custom flags in Xilinx zynq firmware - Various small fixes to the Xilinx clk driver - A single minor rounding fix for the legacy Allwinner clock support - A few patches from Abel Vesa as preparation of adding audiomix clock support on i.MX - A couple of cleanups from Anson Huang for i.MX clk-sscg-pll and clk-pllv3 drivers - Drop dependency on ARM64 for i.MX8M clock driver, to support aarch32 mode on aarch64 hardware - A series from Peng Fan to improve i.MX8M clock drivers, using composite clock for core and bus clk slice - Set a better parent clock for flexcan on i.MX6UL to support CiA102 defined bit rates - A couple changes for EMC frequency scaling on Tegra210 - Support for CPU frequency scaling on Tegra20/Tegra30 - New clk gate for CSI test pattern generator on Tegra210 - Regression fixes for Samsung exynos542x and exynos5433 SoCs - Use of fallthrough; attribute for Samsung s3c24xx - Updates and fixup HDMI and video clocks on Meson8b - Fixup reset polarity on Meson8b - Fix GPU glitch free mux switch on Meson gx and g12 - A minor fix for the currently unused suspend/resume handling on Renesas RZ/A1 and RZ/A2 - Two more conversions of Renesas DT bindings to json-schema - Add support for the USB 2.0 clock selector on Renesas R-Car M3-W+" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (155 commits) clk: mediatek: Remove ifr{0,1}_cfg_regs structures clk: baikal-t1: remove redundant assignment to variable 'divider' clk: baikal-t1: fix spelling mistake "Uncompatible" -> "Incompatible" dt-bindings: clock: Add a missing include to MMP Audio Clock binding dt: Add bindings for IDT VersaClock 5P49V5925 clk: vc5: Add support for IDT VersaClock 5P49V6965 clk: Add Baikal-T1 CCU Dividers driver clk: Add Baikal-T1 CCU PLLs driver dt-bindings: clk: Add Baikal-T1 CCU Dividers binding dt-bindings: clk: Add Baikal-T1 CCU PLLs binding clk: mediatek: assign the initial value to clk_init_data of mtk_mux clk: mediatek: Add MT6765 clock support clk: mediatek: add mt6765 clock IDs dt-bindings: clock: mediatek: document clk bindings vcodecsys for Mediatek MT6765 SoC dt-bindings: clock: mediatek: document clk bindings mipi0a for Mediatek MT6765 SoC dt-bindings: clock: mediatek: document clk bindings for Mediatek MT6765 SoC CLK: HSDK: CGU: add support for 148.5MHz clock CLK: HSDK: CGU: support PLL bypassing CLK: HSDK: CGU: check if PLL is bypassed first clk: clk-si5341: Add support for the Si5345 series ...
266 lines
6.2 KiB
C
266 lines
6.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __MACH_MMP_CLK_H
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#define __MACH_MMP_CLK_H
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#include <linux/clk-provider.h>
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#include <linux/pm_domain.h>
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#include <linux/clkdev.h>
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#define APBC_NO_BUS_CTRL BIT(0)
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#define APBC_POWER_CTRL BIT(1)
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/* Clock type "factor" */
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struct mmp_clk_factor_masks {
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unsigned int factor;
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unsigned int num_mask;
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unsigned int den_mask;
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unsigned int num_shift;
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unsigned int den_shift;
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unsigned int enable_mask;
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};
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struct mmp_clk_factor_tbl {
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unsigned int num;
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unsigned int den;
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};
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struct mmp_clk_factor {
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struct clk_hw hw;
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void __iomem *base;
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struct mmp_clk_factor_masks *masks;
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struct mmp_clk_factor_tbl *ftbl;
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unsigned int ftbl_cnt;
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spinlock_t *lock;
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};
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extern struct clk *mmp_clk_register_factor(const char *name,
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const char *parent_name, unsigned long flags,
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void __iomem *base, struct mmp_clk_factor_masks *masks,
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struct mmp_clk_factor_tbl *ftbl, unsigned int ftbl_cnt,
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spinlock_t *lock);
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/* Clock type "mix" */
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#define MMP_CLK_BITS_MASK(width, shift) \
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(((1 << (width)) - 1) << (shift))
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#define MMP_CLK_BITS_GET_VAL(data, width, shift) \
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((data & MMP_CLK_BITS_MASK(width, shift)) >> (shift))
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#define MMP_CLK_BITS_SET_VAL(val, width, shift) \
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(((val) << (shift)) & MMP_CLK_BITS_MASK(width, shift))
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enum {
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MMP_CLK_MIX_TYPE_V1,
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MMP_CLK_MIX_TYPE_V2,
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MMP_CLK_MIX_TYPE_V3,
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};
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/* The register layout */
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struct mmp_clk_mix_reg_info {
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void __iomem *reg_clk_ctrl;
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void __iomem *reg_clk_sel;
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u8 width_div;
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u8 shift_div;
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u8 width_mux;
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u8 shift_mux;
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u8 bit_fc;
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};
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/* The suggested clock table from user. */
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struct mmp_clk_mix_clk_table {
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unsigned long rate;
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u8 parent_index;
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unsigned int divisor;
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unsigned int valid;
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};
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struct mmp_clk_mix_config {
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struct mmp_clk_mix_reg_info reg_info;
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struct mmp_clk_mix_clk_table *table;
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unsigned int table_size;
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u32 *mux_table;
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struct clk_div_table *div_table;
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u8 div_flags;
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u8 mux_flags;
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};
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struct mmp_clk_mix {
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struct clk_hw hw;
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struct mmp_clk_mix_reg_info reg_info;
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struct mmp_clk_mix_clk_table *table;
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u32 *mux_table;
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struct clk_div_table *div_table;
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unsigned int table_size;
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u8 div_flags;
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u8 mux_flags;
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unsigned int type;
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spinlock_t *lock;
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};
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extern const struct clk_ops mmp_clk_mix_ops;
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extern struct clk *mmp_clk_register_mix(struct device *dev,
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const char *name,
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const char * const *parent_names,
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u8 num_parents,
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unsigned long flags,
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struct mmp_clk_mix_config *config,
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spinlock_t *lock);
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/* Clock type "gate". MMP private gate */
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#define MMP_CLK_GATE_NEED_DELAY BIT(0)
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struct mmp_clk_gate {
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struct clk_hw hw;
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void __iomem *reg;
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u32 mask;
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u32 val_enable;
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u32 val_disable;
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unsigned int flags;
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spinlock_t *lock;
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};
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extern const struct clk_ops mmp_clk_gate_ops;
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extern struct clk *mmp_clk_register_gate(struct device *dev, const char *name,
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const char *parent_name, unsigned long flags,
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void __iomem *reg, u32 mask, u32 val_enable,
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u32 val_disable, unsigned int gate_flags,
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spinlock_t *lock);
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extern struct clk *mmp_clk_register_apbc(const char *name,
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const char *parent_name, void __iomem *base,
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unsigned int delay, unsigned int apbc_flags, spinlock_t *lock);
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extern struct clk *mmp_clk_register_apmu(const char *name,
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const char *parent_name, void __iomem *base, u32 enable_mask,
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spinlock_t *lock);
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struct mmp_clk_unit {
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unsigned int nr_clks;
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struct clk **clk_table;
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struct clk_onecell_data clk_data;
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};
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struct mmp_param_fixed_rate_clk {
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unsigned int id;
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char *name;
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const char *parent_name;
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unsigned long flags;
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unsigned long fixed_rate;
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};
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void mmp_register_fixed_rate_clks(struct mmp_clk_unit *unit,
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struct mmp_param_fixed_rate_clk *clks,
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int size);
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struct mmp_param_fixed_factor_clk {
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unsigned int id;
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char *name;
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const char *parent_name;
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unsigned long mult;
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unsigned long div;
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unsigned long flags;
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};
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void mmp_register_fixed_factor_clks(struct mmp_clk_unit *unit,
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struct mmp_param_fixed_factor_clk *clks,
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int size);
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struct mmp_param_general_gate_clk {
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unsigned int id;
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const char *name;
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const char *parent_name;
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unsigned long flags;
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unsigned long offset;
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u8 bit_idx;
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u8 gate_flags;
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spinlock_t *lock;
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};
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void mmp_register_general_gate_clks(struct mmp_clk_unit *unit,
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struct mmp_param_general_gate_clk *clks,
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void __iomem *base, int size);
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struct mmp_param_gate_clk {
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unsigned int id;
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char *name;
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const char *parent_name;
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unsigned long flags;
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unsigned long offset;
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u32 mask;
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u32 val_enable;
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u32 val_disable;
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unsigned int gate_flags;
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spinlock_t *lock;
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};
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void mmp_register_gate_clks(struct mmp_clk_unit *unit,
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struct mmp_param_gate_clk *clks,
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void __iomem *base, int size);
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struct mmp_param_mux_clk {
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unsigned int id;
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char *name;
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const char * const *parent_name;
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u8 num_parents;
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unsigned long flags;
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unsigned long offset;
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u8 shift;
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u8 width;
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u8 mux_flags;
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spinlock_t *lock;
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};
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void mmp_register_mux_clks(struct mmp_clk_unit *unit,
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struct mmp_param_mux_clk *clks,
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void __iomem *base, int size);
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struct mmp_param_div_clk {
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unsigned int id;
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char *name;
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const char *parent_name;
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unsigned long flags;
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unsigned long offset;
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u8 shift;
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u8 width;
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u8 div_flags;
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spinlock_t *lock;
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};
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void mmp_register_div_clks(struct mmp_clk_unit *unit,
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struct mmp_param_div_clk *clks,
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void __iomem *base, int size);
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struct mmp_param_pll_clk {
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unsigned int id;
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char *name;
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unsigned long default_rate;
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unsigned long enable_offset;
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u32 enable;
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unsigned long offset;
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u8 shift;
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/* MMP3 specific: */
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unsigned long input_rate;
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unsigned long postdiv_offset;
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unsigned long postdiv_shift;
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};
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void mmp_register_pll_clks(struct mmp_clk_unit *unit,
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struct mmp_param_pll_clk *clks,
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void __iomem *base, int size);
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#define DEFINE_MIX_REG_INFO(w_d, s_d, w_m, s_m, fc) \
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{ \
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.width_div = (w_d), \
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.shift_div = (s_d), \
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.width_mux = (w_m), \
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.shift_mux = (s_m), \
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.bit_fc = (fc), \
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}
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void mmp_clk_init(struct device_node *np, struct mmp_clk_unit *unit,
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int nr_clks);
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void mmp_clk_add(struct mmp_clk_unit *unit, unsigned int id,
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struct clk *clk);
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/* Power islands */
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#define MMP_PM_DOMAIN_NO_DISABLE BIT(0)
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struct generic_pm_domain *mmp_pm_domain_register(const char *name,
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void __iomem *reg,
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u32 power_on, u32 reset, u32 clock_enable,
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unsigned int flags, spinlock_t *lock);
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#endif
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