forked from Minki/linux
742b50f9dc
The newly added function is only built into the kernel if mmp2
is enabled, causing a link error otherwise.
arm-linux-gnueabi-ld: drivers/clk/mmp/clk.o: in function `mmp_register_pll_clks':
clk.c:(.text+0x6dc): undefined reference to `mmp_clk_register_pll'
Move it to a different file to get it to link.
Fixes: 5d34d0b32d
("clk: mmp2: Add support for PLL clock sources")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lkml.kernel.org/r/20200408160518.2798571-1-arnd@arndb.de
Reported-by: Guenter Roeck <linux@roeck-us.net>
Reported-by: kbuild test robot <lkp@intel.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
171 lines
3.5 KiB
C
171 lines
3.5 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* MMP PLL clock rate calculation
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*
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* Copyright (C) 2020 Lubomir Rintel <lkundrak@v3.sk>
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*/
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#include <linux/clk-provider.h>
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#include <linux/slab.h>
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#include <linux/io.h>
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#include "clk.h"
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#define to_clk_mmp_pll(hw) container_of(hw, struct mmp_clk_pll, hw)
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struct mmp_clk_pll {
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struct clk_hw hw;
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unsigned long default_rate;
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void __iomem *enable_reg;
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u32 enable;
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void __iomem *reg;
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u8 shift;
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unsigned long input_rate;
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void __iomem *postdiv_reg;
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u8 postdiv_shift;
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};
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static int mmp_clk_pll_is_enabled(struct clk_hw *hw)
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{
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struct mmp_clk_pll *pll = to_clk_mmp_pll(hw);
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u32 val;
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val = readl_relaxed(pll->enable_reg);
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if ((val & pll->enable) == pll->enable)
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return 1;
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/* Some PLLs, if not software controlled, output default clock. */
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if (pll->default_rate > 0)
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return 1;
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return 0;
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}
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static unsigned long mmp_clk_pll_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct mmp_clk_pll *pll = to_clk_mmp_pll(hw);
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u32 fbdiv, refdiv, postdiv;
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u64 rate;
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u32 val;
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val = readl_relaxed(pll->enable_reg);
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if ((val & pll->enable) != pll->enable)
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return pll->default_rate;
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if (pll->reg) {
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val = readl_relaxed(pll->reg);
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fbdiv = (val >> pll->shift) & 0x1ff;
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refdiv = (val >> (pll->shift + 9)) & 0x1f;
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} else {
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fbdiv = 2;
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refdiv = 1;
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}
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if (pll->postdiv_reg) {
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/* MMP3 clock rate calculation */
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static const u8 postdivs[] = {2, 3, 4, 5, 6, 8, 10, 12, 16};
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val = readl_relaxed(pll->postdiv_reg);
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postdiv = (val >> pll->postdiv_shift) & 0x7;
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rate = pll->input_rate;
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rate *= 2 * fbdiv;
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do_div(rate, refdiv);
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do_div(rate, postdivs[postdiv]);
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} else {
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/* MMP2 clock rate calculation */
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if (refdiv == 3) {
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rate = 19200000;
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} else if (refdiv == 4) {
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rate = 26000000;
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} else {
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pr_err("bad refdiv: %d (0x%08x)\n", refdiv, val);
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return 0;
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}
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rate *= fbdiv + 2;
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do_div(rate, refdiv + 2);
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}
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return (unsigned long)rate;
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}
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static const struct clk_ops mmp_clk_pll_ops = {
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.is_enabled = mmp_clk_pll_is_enabled,
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.recalc_rate = mmp_clk_pll_recalc_rate,
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};
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static struct clk *mmp_clk_register_pll(char *name,
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unsigned long default_rate,
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void __iomem *enable_reg, u32 enable,
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void __iomem *reg, u8 shift,
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unsigned long input_rate,
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void __iomem *postdiv_reg, u8 postdiv_shift)
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{
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struct mmp_clk_pll *pll;
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struct clk *clk;
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struct clk_init_data init;
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pll = kzalloc(sizeof(*pll), GFP_KERNEL);
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if (!pll)
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return ERR_PTR(-ENOMEM);
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init.name = name;
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init.ops = &mmp_clk_pll_ops;
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init.flags = 0;
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init.parent_names = NULL;
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init.num_parents = 0;
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pll->default_rate = default_rate;
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pll->enable_reg = enable_reg;
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pll->enable = enable;
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pll->reg = reg;
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pll->shift = shift;
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pll->input_rate = input_rate;
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pll->postdiv_reg = postdiv_reg;
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pll->postdiv_shift = postdiv_shift;
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pll->hw.init = &init;
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clk = clk_register(NULL, &pll->hw);
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if (IS_ERR(clk))
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kfree(pll);
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return clk;
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}
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void mmp_register_pll_clks(struct mmp_clk_unit *unit,
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struct mmp_param_pll_clk *clks,
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void __iomem *base, int size)
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{
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struct clk *clk;
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int i;
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for (i = 0; i < size; i++) {
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void __iomem *reg = NULL;
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if (clks[i].offset)
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reg = base + clks[i].offset;
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clk = mmp_clk_register_pll(clks[i].name,
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clks[i].default_rate,
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base + clks[i].enable_offset,
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clks[i].enable,
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reg, clks[i].shift,
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clks[i].input_rate,
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base + clks[i].postdiv_offset,
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clks[i].postdiv_shift);
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if (IS_ERR(clk)) {
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pr_err("%s: failed to register clock %s\n",
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__func__, clks[i].name);
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continue;
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}
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if (clks[i].id)
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unit->clk_table[clks[i].id] = clk;
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}
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}
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