5fd39dc220
This change exposes write-combine mappings under sysfs for prefetchable PCI resources on arm64. Originally, the usage of "write combine" here was driven by the x86 definition of write combine. This definition is specific to x86 and does not generalize to other architectures. However, the usage of WC has mutated to "write combine" semantics, which is implemented differently on each arch. Generally, prefetchable BARs are accepted to allow speculative accesses, write combining, and re-ordering-- from the PCI perspective, this means there are no read side effects. (This contradicts the PCI spec which allows prefetchable BARs to have read side effects, but this definition is ill-advised as it is impossible to meet.) On x86, prefetchable BARs are mapped as WC as originally defined (with some conditionals on arch features). On arm64, WC is taken to mean normal non-cacheable memory. In practice, write combine semantics are used to minimize write operations. A common usage of this is minimizing PCI TLPs which can significantly improve performance with PCI devices. In order to provide the same benefits to userspace, we need to allow userspace to map prefetchable BARs with write combine semantics. The resourceX_wc mapping is used today by userspace programs and libraries. While this model is flawed as "write combine" is very ill-defined, it is already used by multiple non-x86 archs to expose write combine semantics to user space. We enable this on arm64 to give userspace on arm64 an equivalent mechanism for utilizing write combining with PCI devices. Signed-off-by: Clint Sbisa <csbisa@amazon.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Ard Biesheuvel <ardb@kernel.org> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Bjorn Helgaas <helgaas@kernel.org> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Jason Gunthorpe <jgg@nvidia.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Will Deacon <will@kernel.org> Link: https://lore.kernel.org/r/20200918033312.ddfpibgfylfjpex2@amazon.com Signed-off-by: Will Deacon <will@kernel.org>
39 lines
764 B
C
39 lines
764 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __ASM_PCI_H
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#define __ASM_PCI_H
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#include <linux/types.h>
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#include <linux/slab.h>
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#include <linux/dma-mapping.h>
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#include <asm/io.h>
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#define PCIBIOS_MIN_IO 0x1000
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#define PCIBIOS_MIN_MEM 0
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/*
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* Set to 1 if the kernel should re-assign all PCI bus numbers
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*/
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#define pcibios_assign_all_busses() \
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(pci_has_flag(PCI_REASSIGN_ALL_BUS))
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#define arch_can_pci_mmap_wc() 1
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#define ARCH_GENERIC_PCI_MMAP_RESOURCE 1
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extern int isa_dma_bridge_buggy;
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#ifdef CONFIG_PCI
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static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
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{
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/* no legacy IRQ on arm64 */
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return -ENODEV;
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}
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static inline int pci_proc_domain(struct pci_bus *bus)
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{
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return 1;
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}
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#endif /* CONFIG_PCI */
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#endif /* __ASM_PCI_H */
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