forked from Minki/linux
f21fb3ed36
Following patch V8 adds support for Cavium Liquidio pci express based 10Gig ethernet adapters. 1) Consolidated all debug macros to either call dev_* or netdev_* macros directly, feedback from previous patch. 2) Changed soft commands to avoid crash when running in interrupt context. 3) Fixed link status not reflecting correct status when NetworkManager is running. Added MODULE_FIRMWARE declarations. Following were the previous patches. Patch V7: 1) Minor comments from v6 release regarding debug statements. 2) Fix for large multicast lists. 3) Fixed lockup issue if port initialization fails. 4) Enabled MSI by default. https://patchwork.ozlabs.org/patch/464441/ Patch V6: 1) Addressed the uint64 vs u64 issue, feedback from previous patch. 2) Consolidated some receive processing routines. 3) Removed link status polling method. https://patchwork.ozlabs.org/patch/459514/ Patch V5: Based on the feedback from earlier patches with regards to consolidation of common functions like device init, register programming for cn66xx and cn68xx devices. https://patchwork.ozlabs.org/patch/438979/ Patch V4: Following were the changes based on the feedback from earlier patch: 1) Added mmiowb while synchronizing queue updates and other hw interactions. 2) Statistics will now be incremented non-atomically per each ring. liquidio_get_stats will add stats of each ring while reporting the total statistics counts. 3) Modified liquidio_ioctl to return proper return codes. 4) Modified device naming to use standard Ethernet naming. 5) Global function names in the driver will have lio_/liquidio_/octeon_ prefix. 6) Ethtool related changes for: Removed redundant stats and jiffies. Use default ethtool handler of link status. Speed setting will make use of ethtool_cmd_speed_set. 7) Added checks for pci_map_* return codes. 8) Check for signals while waiting in interruptible mode https://patchwork.ozlabs.org/patch/435073/ Patch v3: Implemented feedback from previous patch like: Removed NAPI Config and DEBUG config options, added BQL and xmit_more support. https://patchwork.ozlabs.org/patch/422749/ Patch V2: Implemented feedback from previous patch. https://patchwork.ozlabs.org/patch/413539/ First Patch: https://patchwork.ozlabs.org/patch/412946/ Signed-off-by: Derek Chickles <derek.chickles@caviumnetworks.com> Signed-off-by: Satanand Burla <satananda.burla@caviumnetworks.com> Signed-off-by: Felix Manlunas <felix.manlunas@caviumnetworks.com> Signed-off-by: Robert Richter <Robert.Richter@caviumnetworks.com> Signed-off-by: Aleksey Makarov <Aleksey.Makarov@caviumnetworks.com> Signed-off-by: Raghu Vatsavayi <raghu.vatsavayi@caviumnetworks.com> Signed-off-by: David S. Miller <davem@davemloft.net>
76 lines
2.4 KiB
C
76 lines
2.4 KiB
C
/**********************************************************************
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* Author: Cavium, Inc.
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*
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* Contact: support@cavium.com
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* Please include "LiquidIO" in the subject.
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*
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* Copyright (c) 2003-2015 Cavium, Inc.
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*
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* This file is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, Version 2, as
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* published by the Free Software Foundation.
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*
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* This file is distributed in the hope that it will be useful, but
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* AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
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* NONINFRINGEMENT. See the GNU General Public License for more
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* details.
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*
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* This file may also be available under a different license from Cavium.
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* Contact Cavium, Inc. for more information
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**********************************************************************/
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/*! \file octeon_mem_ops.h
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* \brief Host Driver: Routines used to read/write Octeon memory.
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*/
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#ifndef __OCTEON_MEM_OPS_H__
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#define __OCTEON_MEM_OPS_H__
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/** Read a 64-bit value from a BAR1 mapped core memory address.
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* @param oct - pointer to the octeon device.
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* @param core_addr - the address to read from.
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*
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* The range_idx gives the BAR1 index register for the range of address
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* in which core_addr is mapped.
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*
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* @return 64-bit value read from Core memory
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*/
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u64 octeon_read_device_mem64(struct octeon_device *oct, u64 core_addr);
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/** Read a 32-bit value from a BAR1 mapped core memory address.
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* @param oct - pointer to the octeon device.
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* @param core_addr - the address to read from.
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*
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* @return 32-bit value read from Core memory
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*/
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u32 octeon_read_device_mem32(struct octeon_device *oct, u64 core_addr);
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/** Write a 32-bit value to a BAR1 mapped core memory address.
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* @param oct - pointer to the octeon device.
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* @param core_addr - the address to write to.
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* @param val - 32-bit value to write.
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*/
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void
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octeon_write_device_mem32(struct octeon_device *oct,
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u64 core_addr,
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u32 val);
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/** Read multiple bytes from Octeon memory.
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*/
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void
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octeon_pci_read_core_mem(struct octeon_device *oct,
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u64 coreaddr,
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u8 *buf,
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u32 len);
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/** Write multiple bytes into Octeon memory.
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*/
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void
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octeon_pci_write_core_mem(struct octeon_device *oct,
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u64 coreaddr,
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u8 *buf,
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u32 len);
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#endif
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