Andrzej Hajda 4677f51ade drm/exynos/hdmi: fix PHY configuration sequence ... Proper PHY configuration should be as follow: 1. set HDMI clock parents to OSCCLK. 2. reconfigure PHY. 3. set HDMI clock parents to PHY. 4. wait for PLL stabilization. The patch fixes it and consolidates the code. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>		2016-04-30 01:03:54 +09:00
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drm	drm/exynos/hdmi: fix PHY configuration sequence	2016-04-30 01:03:54 +09:00
host1x	Merge branch 'drm-next' of git://people.freedesktop.org/~airlied/linux	2016-03-21 13:48:00 -07:00
ipu-v3	gpu: ipu-v3: ipu-dmfc: Rename ipu_dmfc_init_channel to ipu_dmfc_config_wait4eot	2016-03-31 11:24:33 +02:00
vga	vga_switcheroo: Add support for switching only the DDC	2016-02-09 11:21:07 +01:00
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