Michael Tretter 4472e1849d soc: xilinx: vcu: make pll post divider explicit ... According to the downstream driver documentation due to timing constraints the output divider of the PLL has to be set to 1/2. Add a helper function for that check instead of burying the code in one large setup function. The bit is undocumented and marked as reserved in the register reference. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Acked-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/20210121071659.1226489-10-m.tretter@pengutronix.de Signed-off-by: Stephen Boyd <sboyd@kernel.org>		2021-02-08 18:31:25 -08:00
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Kconfig	soc: xilinx: vcu: register PLL as fixed rate clock	2021-02-08 18:31:25 -08:00
Makefile	drivers: soc: xilinx: Add ZynqMP power domain driver	2019-02-12 13:38:16 +01:00
xlnx_vcu.c	soc: xilinx: vcu: make pll post divider explicit	2021-02-08 18:31:25 -08:00
zynqmp_pm_domains.c	firmware: xilinx: Remove eemi ops for set_requirement	2020-04-28 15:45:09 +02:00
zynqmp_power.c	soc: xilinx: Fix error code in zynqmp_pm_probe()	2020-06-18 10:07:17 +02:00