linux/drivers/gpu/drm/amd/display
Alvin Lee 4453fbec10 drm/amd/display: Separate pipe disconnect from rest of progrmaming
[Why]
When changing pixel formats for HDR (e.g. ARGB -> FP16)
there are configurations that change from 2 pipes to 1 pipe.
In these cases, it seems that disconnecting MPCC and doing
a surface update at the same time(after unlocking) causes
some registers to be updated slightly faster than others
after unlocking (e.g. if the pixel format is updated to FP16
before the new surface address is programmed, we get
corruption on the screen because the pixel formats aren't
matching). We separate disconnecting MPCC from the rest
of  the  pipe programming sequence to prevent this.

[How]
Move MPCC disconnect into separate operation than the
rest of the pipe programming.

Signed-off-by: Alvin Lee <alvin.lee2@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-08-04 17:29:28 -04:00
..
amdgpu_dm drm/amd/display: Add debugfs for forcing stream timing sync 2020-08-04 17:29:28 -04:00
dc drm/amd/display: Separate pipe disconnect from rest of progrmaming 2020-08-04 17:29:28 -04:00
dmub drm/amd/display: [FW Promotion] Release 0.0.26 2020-07-30 14:13:20 -04:00
include drm/amd/display: add asics info for SI parts 2020-07-27 16:45:44 -04:00
modules drm/amd/display: Allow asic specific FSFT timing optimization 2020-07-30 14:13:04 -04:00
Kconfig drm/amd/display: enable SI support in the Kconfig (v2) 2020-07-28 09:22:57 -04:00
Makefile drm/amd/display: Drop CONFIG_DRM_AMD_DC_DMUB guards 2019-11-13 15:29:42 -05:00
TODO