forked from Minki/linux
05fb05a6ca
When changing the active bit from an MMIO trap, we decide to explode if the intid is that of a private interrupt. This flawed logic comes from the fact that we were assuming that kvm_vcpu_kick() as called by kvm_arm_halt_vcpu() would not return before the called vcpu responded, but this is not the case, so we need to perform this wait even for private interrupts. Dropping the BUG_ON seems like the right thing to do. [ Commit message tweaked by Christoffer ] Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
525 lines
13 KiB
C
525 lines
13 KiB
C
/*
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* VGIC MMIO handling functions
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/bitops.h>
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#include <linux/bsearch.h>
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#include <linux/kvm.h>
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#include <linux/kvm_host.h>
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#include <kvm/iodev.h>
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#include <kvm/arm_vgic.h>
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#include "vgic.h"
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#include "vgic-mmio.h"
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unsigned long vgic_mmio_read_raz(struct kvm_vcpu *vcpu,
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gpa_t addr, unsigned int len)
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{
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return 0;
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}
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unsigned long vgic_mmio_read_rao(struct kvm_vcpu *vcpu,
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gpa_t addr, unsigned int len)
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{
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return -1UL;
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}
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void vgic_mmio_write_wi(struct kvm_vcpu *vcpu, gpa_t addr,
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unsigned int len, unsigned long val)
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{
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/* Ignore */
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}
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/*
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* Read accesses to both GICD_ICENABLER and GICD_ISENABLER return the value
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* of the enabled bit, so there is only one function for both here.
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*/
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unsigned long vgic_mmio_read_enable(struct kvm_vcpu *vcpu,
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gpa_t addr, unsigned int len)
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{
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u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
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u32 value = 0;
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int i;
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/* Loop over all IRQs affected by this read */
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for (i = 0; i < len * 8; i++) {
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struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
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if (irq->enabled)
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value |= (1U << i);
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}
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return value;
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}
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void vgic_mmio_write_senable(struct kvm_vcpu *vcpu,
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gpa_t addr, unsigned int len,
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unsigned long val)
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{
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u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
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int i;
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for_each_set_bit(i, &val, len * 8) {
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struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
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spin_lock(&irq->irq_lock);
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irq->enabled = true;
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vgic_queue_irq_unlock(vcpu->kvm, irq);
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}
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}
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void vgic_mmio_write_cenable(struct kvm_vcpu *vcpu,
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gpa_t addr, unsigned int len,
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unsigned long val)
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{
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u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
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int i;
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for_each_set_bit(i, &val, len * 8) {
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struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
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spin_lock(&irq->irq_lock);
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irq->enabled = false;
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spin_unlock(&irq->irq_lock);
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}
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}
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unsigned long vgic_mmio_read_pending(struct kvm_vcpu *vcpu,
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gpa_t addr, unsigned int len)
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{
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u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
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u32 value = 0;
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int i;
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/* Loop over all IRQs affected by this read */
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for (i = 0; i < len * 8; i++) {
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struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
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if (irq->pending)
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value |= (1U << i);
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}
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return value;
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}
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void vgic_mmio_write_spending(struct kvm_vcpu *vcpu,
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gpa_t addr, unsigned int len,
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unsigned long val)
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{
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u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
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int i;
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for_each_set_bit(i, &val, len * 8) {
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struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
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spin_lock(&irq->irq_lock);
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irq->pending = true;
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if (irq->config == VGIC_CONFIG_LEVEL)
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irq->soft_pending = true;
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vgic_queue_irq_unlock(vcpu->kvm, irq);
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}
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}
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void vgic_mmio_write_cpending(struct kvm_vcpu *vcpu,
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gpa_t addr, unsigned int len,
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unsigned long val)
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{
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u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
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int i;
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for_each_set_bit(i, &val, len * 8) {
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struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
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spin_lock(&irq->irq_lock);
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if (irq->config == VGIC_CONFIG_LEVEL) {
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irq->soft_pending = false;
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irq->pending = irq->line_level;
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} else {
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irq->pending = false;
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}
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spin_unlock(&irq->irq_lock);
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}
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}
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unsigned long vgic_mmio_read_active(struct kvm_vcpu *vcpu,
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gpa_t addr, unsigned int len)
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{
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u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
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u32 value = 0;
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int i;
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/* Loop over all IRQs affected by this read */
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for (i = 0; i < len * 8; i++) {
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struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
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if (irq->active)
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value |= (1U << i);
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}
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return value;
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}
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static void vgic_mmio_change_active(struct kvm_vcpu *vcpu, struct vgic_irq *irq,
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bool new_active_state)
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{
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spin_lock(&irq->irq_lock);
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/*
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* If this virtual IRQ was written into a list register, we
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* have to make sure the CPU that runs the VCPU thread has
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* synced back LR state to the struct vgic_irq. We can only
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* know this for sure, when either this irq is not assigned to
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* anyone's AP list anymore, or the VCPU thread is not
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* running on any CPUs.
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*
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* In the opposite case, we know the VCPU thread may be on its
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* way back from the guest and still has to sync back this
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* IRQ, so we release and re-acquire the spin_lock to let the
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* other thread sync back the IRQ.
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*/
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while (irq->vcpu && /* IRQ may have state in an LR somewhere */
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irq->vcpu->cpu != -1) /* VCPU thread is running */
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cond_resched_lock(&irq->irq_lock);
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irq->active = new_active_state;
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if (new_active_state)
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vgic_queue_irq_unlock(vcpu->kvm, irq);
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else
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spin_unlock(&irq->irq_lock);
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}
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/*
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* If we are fiddling with an IRQ's active state, we have to make sure the IRQ
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* is not queued on some running VCPU's LRs, because then the change to the
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* active state can be overwritten when the VCPU's state is synced coming back
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* from the guest.
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*
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* For shared interrupts, we have to stop all the VCPUs because interrupts can
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* be migrated while we don't hold the IRQ locks and we don't want to be
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* chasing moving targets.
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*
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* For private interrupts, we only have to make sure the single and only VCPU
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* that can potentially queue the IRQ is stopped.
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*/
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static void vgic_change_active_prepare(struct kvm_vcpu *vcpu, u32 intid)
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{
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if (intid < VGIC_NR_PRIVATE_IRQS)
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kvm_arm_halt_vcpu(vcpu);
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else
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kvm_arm_halt_guest(vcpu->kvm);
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}
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/* See vgic_change_active_prepare */
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static void vgic_change_active_finish(struct kvm_vcpu *vcpu, u32 intid)
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{
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if (intid < VGIC_NR_PRIVATE_IRQS)
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kvm_arm_resume_vcpu(vcpu);
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else
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kvm_arm_resume_guest(vcpu->kvm);
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}
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void vgic_mmio_write_cactive(struct kvm_vcpu *vcpu,
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gpa_t addr, unsigned int len,
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unsigned long val)
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{
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u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
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int i;
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vgic_change_active_prepare(vcpu, intid);
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for_each_set_bit(i, &val, len * 8) {
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struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
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vgic_mmio_change_active(vcpu, irq, false);
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}
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vgic_change_active_finish(vcpu, intid);
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}
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void vgic_mmio_write_sactive(struct kvm_vcpu *vcpu,
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gpa_t addr, unsigned int len,
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unsigned long val)
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{
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u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
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int i;
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vgic_change_active_prepare(vcpu, intid);
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for_each_set_bit(i, &val, len * 8) {
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struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
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vgic_mmio_change_active(vcpu, irq, true);
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}
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vgic_change_active_finish(vcpu, intid);
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}
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unsigned long vgic_mmio_read_priority(struct kvm_vcpu *vcpu,
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gpa_t addr, unsigned int len)
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{
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u32 intid = VGIC_ADDR_TO_INTID(addr, 8);
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int i;
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u64 val = 0;
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for (i = 0; i < len; i++) {
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struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
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val |= (u64)irq->priority << (i * 8);
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}
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return val;
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}
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/*
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* We currently don't handle changing the priority of an interrupt that
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* is already pending on a VCPU. If there is a need for this, we would
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* need to make this VCPU exit and re-evaluate the priorities, potentially
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* leading to this interrupt getting presented now to the guest (if it has
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* been masked by the priority mask before).
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*/
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void vgic_mmio_write_priority(struct kvm_vcpu *vcpu,
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gpa_t addr, unsigned int len,
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unsigned long val)
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{
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u32 intid = VGIC_ADDR_TO_INTID(addr, 8);
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int i;
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for (i = 0; i < len; i++) {
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struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
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spin_lock(&irq->irq_lock);
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/* Narrow the priority range to what we actually support */
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irq->priority = (val >> (i * 8)) & GENMASK(7, 8 - VGIC_PRI_BITS);
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spin_unlock(&irq->irq_lock);
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}
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}
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unsigned long vgic_mmio_read_config(struct kvm_vcpu *vcpu,
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gpa_t addr, unsigned int len)
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{
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u32 intid = VGIC_ADDR_TO_INTID(addr, 2);
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u32 value = 0;
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int i;
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for (i = 0; i < len * 4; i++) {
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struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
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if (irq->config == VGIC_CONFIG_EDGE)
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value |= (2U << (i * 2));
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}
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return value;
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}
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void vgic_mmio_write_config(struct kvm_vcpu *vcpu,
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gpa_t addr, unsigned int len,
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unsigned long val)
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{
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u32 intid = VGIC_ADDR_TO_INTID(addr, 2);
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int i;
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for (i = 0; i < len * 4; i++) {
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struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
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/*
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* The configuration cannot be changed for SGIs in general,
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* for PPIs this is IMPLEMENTATION DEFINED. The arch timer
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* code relies on PPIs being level triggered, so we also
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* make them read-only here.
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*/
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if (intid + i < VGIC_NR_PRIVATE_IRQS)
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continue;
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spin_lock(&irq->irq_lock);
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if (test_bit(i * 2 + 1, &val)) {
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irq->config = VGIC_CONFIG_EDGE;
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} else {
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irq->config = VGIC_CONFIG_LEVEL;
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irq->pending = irq->line_level | irq->soft_pending;
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}
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spin_unlock(&irq->irq_lock);
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}
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}
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static int match_region(const void *key, const void *elt)
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{
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const unsigned int offset = (unsigned long)key;
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const struct vgic_register_region *region = elt;
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if (offset < region->reg_offset)
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return -1;
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if (offset >= region->reg_offset + region->len)
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return 1;
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return 0;
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}
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/* Find the proper register handler entry given a certain address offset. */
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static const struct vgic_register_region *
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vgic_find_mmio_region(const struct vgic_register_region *region, int nr_regions,
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unsigned int offset)
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{
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return bsearch((void *)(uintptr_t)offset, region, nr_regions,
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sizeof(region[0]), match_region);
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}
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/*
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* kvm_mmio_read_buf() returns a value in a format where it can be converted
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* to a byte array and be directly observed as the guest wanted it to appear
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* in memory if it had done the store itself, which is LE for the GIC, as the
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* guest knows the GIC is always LE.
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*
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* We convert this value to the CPUs native format to deal with it as a data
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* value.
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*/
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unsigned long vgic_data_mmio_bus_to_host(const void *val, unsigned int len)
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{
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unsigned long data = kvm_mmio_read_buf(val, len);
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switch (len) {
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case 1:
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return data;
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case 2:
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return le16_to_cpu(data);
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case 4:
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return le32_to_cpu(data);
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default:
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return le64_to_cpu(data);
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}
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}
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/*
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* kvm_mmio_write_buf() expects a value in a format such that if converted to
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* a byte array it is observed as the guest would see it if it could perform
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* the load directly. Since the GIC is LE, and the guest knows this, the
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* guest expects a value in little endian format.
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*
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* We convert the data value from the CPUs native format to LE so that the
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* value is returned in the proper format.
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*/
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void vgic_data_host_to_mmio_bus(void *buf, unsigned int len,
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unsigned long data)
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{
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switch (len) {
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case 1:
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break;
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case 2:
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data = cpu_to_le16(data);
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break;
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case 4:
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data = cpu_to_le32(data);
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break;
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default:
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data = cpu_to_le64(data);
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}
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kvm_mmio_write_buf(buf, len, data);
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}
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static
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struct vgic_io_device *kvm_to_vgic_iodev(const struct kvm_io_device *dev)
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{
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return container_of(dev, struct vgic_io_device, dev);
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}
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static bool check_region(const struct vgic_register_region *region,
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gpa_t addr, int len)
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{
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if ((region->access_flags & VGIC_ACCESS_8bit) && len == 1)
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return true;
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if ((region->access_flags & VGIC_ACCESS_32bit) &&
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len == sizeof(u32) && !(addr & 3))
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return true;
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if ((region->access_flags & VGIC_ACCESS_64bit) &&
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len == sizeof(u64) && !(addr & 7))
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return true;
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return false;
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}
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static int dispatch_mmio_read(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
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gpa_t addr, int len, void *val)
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{
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struct vgic_io_device *iodev = kvm_to_vgic_iodev(dev);
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const struct vgic_register_region *region;
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struct kvm_vcpu *r_vcpu;
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unsigned long data;
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region = vgic_find_mmio_region(iodev->regions, iodev->nr_regions,
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addr - iodev->base_addr);
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if (!region || !check_region(region, addr, len)) {
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memset(val, 0, len);
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return 0;
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}
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r_vcpu = iodev->redist_vcpu ? iodev->redist_vcpu : vcpu;
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data = region->read(r_vcpu, addr, len);
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vgic_data_host_to_mmio_bus(val, len, data);
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return 0;
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}
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static int dispatch_mmio_write(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
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gpa_t addr, int len, const void *val)
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{
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struct vgic_io_device *iodev = kvm_to_vgic_iodev(dev);
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const struct vgic_register_region *region;
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struct kvm_vcpu *r_vcpu;
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unsigned long data = vgic_data_mmio_bus_to_host(val, len);
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region = vgic_find_mmio_region(iodev->regions, iodev->nr_regions,
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addr - iodev->base_addr);
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if (!region)
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return 0;
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if (!check_region(region, addr, len))
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return 0;
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r_vcpu = iodev->redist_vcpu ? iodev->redist_vcpu : vcpu;
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region->write(r_vcpu, addr, len, data);
|
|
return 0;
|
|
}
|
|
|
|
struct kvm_io_device_ops kvm_io_gic_ops = {
|
|
.read = dispatch_mmio_read,
|
|
.write = dispatch_mmio_write,
|
|
};
|
|
|
|
int vgic_register_dist_iodev(struct kvm *kvm, gpa_t dist_base_address,
|
|
enum vgic_type type)
|
|
{
|
|
struct vgic_io_device *io_device = &kvm->arch.vgic.dist_iodev;
|
|
int ret = 0;
|
|
unsigned int len;
|
|
|
|
switch (type) {
|
|
case VGIC_V2:
|
|
len = vgic_v2_init_dist_iodev(io_device);
|
|
break;
|
|
#ifdef CONFIG_KVM_ARM_VGIC_V3
|
|
case VGIC_V3:
|
|
len = vgic_v3_init_dist_iodev(io_device);
|
|
break;
|
|
#endif
|
|
default:
|
|
BUG_ON(1);
|
|
}
|
|
|
|
io_device->base_addr = dist_base_address;
|
|
io_device->redist_vcpu = NULL;
|
|
|
|
mutex_lock(&kvm->slots_lock);
|
|
ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, dist_base_address,
|
|
len, &io_device->dev);
|
|
mutex_unlock(&kvm->slots_lock);
|
|
|
|
return ret;
|
|
}
|