forked from Minki/linux
3e70cee46c
Move the PCI 'interrupt-map-mask' and '#interrupt-cells' properties alongside the 'interrupt-map' property in each board dts. This avoids having incomplete set of interrupt properties which may fail validation. Cc: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Rob Herring <robh@kernel.org>
113 lines
2.6 KiB
Plaintext
113 lines
2.6 KiB
Plaintext
// SPDX-License-Identifier: ISC
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/*
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* Device Tree file for ADI Engineering Coyote platform.
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* Derived from boardfiles written by MontaVista software.
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* Ethernet set-up from OpenWrt.
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*/
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/dts-v1/;
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#include "intel-ixp42x.dtsi"
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#include <dt-bindings/input/input.h>
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/ {
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model = "ADI Engineering Coyote reference design";
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compatible = "adieng,coyote", "intel,ixp42x";
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#address-cells = <1>;
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#size-cells = <1>;
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memory@0 {
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/* CHECKME: 16 MB SDRAM minimum, maybe the Coyote actually has more */
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device_type = "memory";
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reg = <0x00000000 0x01000000>;
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};
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chosen {
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bootargs = "console=ttyS0,115200n8 root=/dev/sda1 rw rootwait";
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stdout-path = "uart1:115200n8";
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};
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aliases {
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/* These are switched around */
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serial0 = &uart1;
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serial1 = &uart0;
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};
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soc {
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bus@c4000000 {
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flash@0,0 {
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compatible = "intel,ixp4xx-flash", "cfi-flash";
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bank-width = <2>;
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/*
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* 32 MB of Flash in 128 0x20000 sized blocks
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* mapped in at CS0 and CS1
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*/
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reg = <0 0x00000000 0x2000000>;
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/* Configure expansion bus to allow writes */
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intel,ixp4xx-eb-write-enable = <1>;
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partitions {
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compatible = "redboot-fis";
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/* CHECKME: guess this is Redboot FIS */
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fis-index-block = <0x1ff>;
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};
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};
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};
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pci@c0000000 {
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status = "ok";
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/*
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* Taken from Coyote PCI boardfile.
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* We have slots (IDSEL) 1 and 2 with one assigned IRQ
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* each handling all IRQs.
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*/
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#interrupt-cells = <1>;
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interrupt-map-mask = <0xf800 0 0 7>;
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interrupt-map =
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/* IDSEL 1 */
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<0x0800 0 0 1 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 6 */
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<0x0800 0 0 2 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 1 is irq 6 */
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<0x0800 0 0 3 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 6 */
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<0x0800 0 0 4 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 6 */
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/* IDSEL 2 */
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<0x1000 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 11 */
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<0x1000 0 0 2 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 11 */
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<0x1000 0 0 3 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 11 */
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<0x1000 0 0 4 &gpio0 11 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 2 is irq 11 */
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};
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/* EthB */
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ethernet@c8009000 {
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status = "ok";
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queue-rx = <&qmgr 3>;
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queue-txready = <&qmgr 20>;
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phy-mode = "rgmii";
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phy-handle = <&phy5>;
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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phy4: ethernet-phy@4 {
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reg = <4>;
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};
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phy5: ethernet-phy@5 {
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reg = <5>;
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};
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};
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};
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/* EthC */
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ethernet@c800a000 {
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status = "ok";
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queue-rx = <&qmgr 4>;
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queue-txready = <&qmgr 21>;
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phy-mode = "rgmii";
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phy-handle = <&phy4>;
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};
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};
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};
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