linux/arch/x86/events/intel
Alexey Budankov 421ca868ea perf/x86/intel: Implement LBR callstack context synchronization
Implement intel_pmu_lbr_swap_task_ctx() method updating counters
of the events that requested LBR callstack data on a sample.

The counter can be zero for the case when task context belongs to
a thread that has just come from a block on a futex and the context
contains saved (lbr_stack_state == LBR_VALID) LBR register values.

For the values to be restored at LBR registers on the next thread's
switch-in event it swaps the counter value with the one that is
expected to be non zero at the previous equivalent task perf event
context.

Swap operation type ensures the previous task perf event context
stays consistent with the amount of events that requested LBR
callstack data on a sample.

Signed-off-by: Alexey Budankov <alexey.budankov@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Ian Rogers <irogers@google.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Kan Liang <kan.liang@linux.intel.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Song Liu <songliubraving@fb.com>
Cc: Stephane Eranian <eranian@google.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Vince Weaver <vincent.weaver@maine.edu>
Link: https://lkml.kernel.org/r/261ac742-9022-c3f4-5885-1eae7415b091@linux.intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2019-10-28 12:51:01 +01:00
..
bts.c perf_event: Add support for LSM and SELinux checks 2019-10-17 21:31:55 +02:00
core.c perf_event: Add support for LSM and SELinux checks 2019-10-17 21:31:55 +02:00
cstate.c perf/x86/cstate: Add Tiger Lake CPU support 2019-10-12 15:13:09 +02:00
ds.c perf/x86/intel: Support PEBS output to PT 2019-08-28 11:29:39 +02:00
knc.c License cleanup: add SPDX GPL-2.0 license identifier to files with no license 2017-11-02 11:10:55 +01:00
lbr.c perf/x86/intel: Implement LBR callstack context synchronization 2019-10-28 12:51:01 +01:00
Makefile License cleanup: add SPDX GPL-2.0 license identifier to files with no license 2017-11-02 11:10:55 +01:00
p4.c perf_event: Add support for LSM and SELinux checks 2019-10-17 21:31:55 +02:00
p6.c x86/cpu: Rename cpu_data.x86_mask to cpu_data.x86_stepping 2018-02-15 01:15:52 +01:00
pt.c perf/x86/intel/pt: Fix base for single entry topa 2019-10-20 14:42:28 +02:00
pt.h perf/x86/intel/pt: Get rid of reverse lookup table for ToPA 2019-08-26 12:00:16 +02:00
rapl.c Merge branch 'x86-cpu-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 2019-09-16 18:47:53 -07:00
uncore_nhmex.c perf/x86/intel/uncore: Correct fixed counter index check for NHM 2018-05-31 12:36:28 +02:00
uncore_snb.c perf/x86/intel/uncore: Clean up client IMC 2019-06-17 12:36:21 +02:00
uncore_snbep.c perf/x86/intel/uncore: Add IMC uncore support for Snow Ridge 2019-06-17 12:36:22 +02:00
uncore.c perf/x86/uncore: Fix event group support 2019-10-28 11:02:01 +01:00
uncore.h perf/x86/uncore: Fix event group support 2019-10-28 11:02:01 +01:00