linux/arch/arm64/mm
Yalin Wang 421520ba98 ARM: 8167/1: extend the reserved memory for initrd to be page aligned
This patch extends the start and end address of initrd to be page aligned,
so that we can free all memory including the un-page aligned head or tail
page of initrd, if the start or end address of initrd are not page
aligned, the page can't be freed by free_initrd_mem() function.

Signed-off-by: Yalin Wang <yalin.wang@sonymobile.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-10-02 21:29:17 +01:00
..
cache.S arm64: mm: use inner-shareable barriers for inner-shareable maintenance 2014-05-09 17:21:24 +01:00
context.c arm64: Process management 2012-09-17 13:41:58 +01:00
copypage.c arm64: export __cpu_{clear,copy}_user_page functions 2014-07-08 17:30:51 +01:00
dma-mapping.c arm64: Clean up the default pgprot setting 2014-05-09 15:53:37 +01:00
extable.c arm64: MMU fault handling and page table management 2012-09-17 13:41:57 +01:00
fault.c arm64: mm: Implement 4 levels of translation tables 2014-07-23 15:27:40 +01:00
flush.c arm64: mm: Make icache synchronisation logic huge page aware 2014-07-04 14:26:01 +01:00
hugetlbpage.c hugetlb: restrict hugepage_migration_support() to x86_64 2014-06-04 16:53:51 -07:00
init.c ARM: 8167/1: extend the reserved memory for initrd to be page aligned 2014-10-02 21:29:17 +01:00
ioremap.c arm64: Convert bool ARM64_x_LEVELS to int ARM64_PGTABLE_LEVELS 2014-07-23 15:27:46 +01:00
Makefile arm64: mm: Optimise tlb flush logic where we have >4K granule 2014-05-09 17:00:48 +01:00
mm.h arm64: Remove __flush_dcache_page() 2013-06-07 17:58:30 +01:00
mmap.c mm: remove free_area_cache 2013-07-10 18:11:34 -07:00
mmu.c arm64: mm: Implement 4 levels of translation tables 2014-07-23 15:27:40 +01:00
pgd.c arm64: simplify pgd_alloc 2014-02-05 10:45:07 +00:00
proc-macros.S arm64: mm: use ubfm for dcache_line_size 2014-01-22 16:23:58 +00:00
proc.S arm64: mm: use inner-shareable barriers for inner-shareable maintenance 2014-05-09 17:21:24 +01:00