b21a9c3ee8
We need set-rate-parent flags for the display's clock path so that the DSS driver can change the clock rate of the PLL. This patchs adds the ti,set-rate-parent flag to 'dss_dss_clk' clock node, which is only a gate clock, allowing the setting of the clock rate to propagate to the PLL. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Cc: devicetree@vger.kernel.org Acked-by: Tero Kristo <t-kristo@ti.com> |
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| .. | ||
| bootp | ||
| compressed | ||
| dts | ||
| .gitignore | ||
| install.sh | ||
| Makefile | ||