forked from Minki/linux
d717f7352e
This patch adds sdmmc, sdio, emmc nodes for Rockchip RK3328 SoCs. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
1298 lines
32 KiB
Plaintext
1298 lines
32 KiB
Plaintext
/*
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* Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <dt-bindings/clock/rk3328-cru.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/pinctrl/rockchip.h>
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#include <dt-bindings/power/rk3328-power.h>
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#include <dt-bindings/soc/rockchip,boot-mode.h>
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/ {
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compatible = "rockchip,rk3328";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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serial0 = &uart0;
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serial1 = &uart1;
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serial2 = &uart2;
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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i2c2 = &i2c2;
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i2c3 = &i2c3;
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};
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x0 0x0>;
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clocks = <&cru ARMCLK>;
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enable-method = "psci";
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next-level-cache = <&l2>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x0 0x1>;
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clocks = <&cru ARMCLK>;
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enable-method = "psci";
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next-level-cache = <&l2>;
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x0 0x2>;
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clocks = <&cru ARMCLK>;
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enable-method = "psci";
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next-level-cache = <&l2>;
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};
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cpu3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x0 0x3>;
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clocks = <&cru ARMCLK>;
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enable-method = "psci";
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next-level-cache = <&l2>;
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};
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l2: l2-cache0 {
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compatible = "cache";
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};
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};
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amba {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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dmac: dmac@ff1f0000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0x0 0xff1f0000 0x0 0x4000>;
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru ACLK_DMAC>;
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clock-names = "apb_pclk";
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#dma-cells = <1>;
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};
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};
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arm-pmu {
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compatible = "arm,cortex-a53-pmu";
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interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
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};
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psci {
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compatible = "arm,psci-1.0", "arm,psci-0.2";
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method = "smc";
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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};
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xin24m: xin24m {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <24000000>;
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clock-output-names = "xin24m";
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};
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grf: syscon@ff100000 {
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compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
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reg = <0x0 0xff100000 0x0 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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power: power-controller {
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compatible = "rockchip,rk3328-power-controller";
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#power-domain-cells = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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pd_hevc@RK3328_PD_HEVC {
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reg = <RK3328_PD_HEVC>;
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};
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pd_video@RK3328_PD_VIDEO {
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reg = <RK3328_PD_VIDEO>;
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};
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pd_vpu@RK3328_PD_VPU {
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reg = <RK3328_PD_VPU>;
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};
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};
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reboot-mode {
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compatible = "syscon-reboot-mode";
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offset = <0x5c8>;
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mode-normal = <BOOT_NORMAL>;
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mode-recovery = <BOOT_RECOVERY>;
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mode-bootloader = <BOOT_FASTBOOT>;
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mode-loader = <BOOT_BL_DOWNLOAD>;
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};
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};
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uart0: serial@ff110000 {
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compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
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reg = <0x0 0xff110000 0x0 0x100>;
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interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
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clock-names = "baudclk", "apb_pclk";
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dmas = <&dmac 2>, <&dmac 3>;
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#dma-cells = <2>;
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
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reg-io-width = <4>;
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reg-shift = <2>;
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status = "disabled";
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};
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uart1: serial@ff120000 {
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compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
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reg = <0x0 0xff120000 0x0 0x100>;
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interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
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clock-names = "sclk_uart", "pclk_uart";
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dmas = <&dmac 4>, <&dmac 5>;
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#dma-cells = <2>;
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pinctrl-names = "default";
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pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
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reg-io-width = <4>;
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reg-shift = <2>;
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status = "disabled";
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};
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uart2: serial@ff130000 {
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compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
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reg = <0x0 0xff130000 0x0 0x100>;
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interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
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clock-names = "baudclk", "apb_pclk";
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dmas = <&dmac 6>, <&dmac 7>;
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#dma-cells = <2>;
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pinctrl-names = "default";
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pinctrl-0 = <&uart2m1_xfer>;
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reg-io-width = <4>;
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reg-shift = <2>;
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status = "disabled";
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};
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i2c0: i2c@ff150000 {
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compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
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reg = <0x0 0xff150000 0x0 0x1000>;
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interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
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clock-names = "i2c", "pclk";
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pinctrl-names = "default";
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pinctrl-0 = <&i2c0_xfer>;
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status = "disabled";
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};
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i2c1: i2c@ff160000 {
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compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
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reg = <0x0 0xff160000 0x0 0x1000>;
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interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
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clock-names = "i2c", "pclk";
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pinctrl-names = "default";
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pinctrl-0 = <&i2c1_xfer>;
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status = "disabled";
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};
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i2c2: i2c@ff170000 {
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compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
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reg = <0x0 0xff170000 0x0 0x1000>;
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interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
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clock-names = "i2c", "pclk";
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pinctrl-names = "default";
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pinctrl-0 = <&i2c2_xfer>;
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status = "disabled";
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};
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i2c3: i2c@ff180000 {
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compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
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reg = <0x0 0xff180000 0x0 0x1000>;
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interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
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clock-names = "i2c", "pclk";
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pinctrl-names = "default";
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pinctrl-0 = <&i2c3_xfer>;
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status = "disabled";
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};
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spi0: spi@ff190000 {
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compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi";
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reg = <0x0 0xff190000 0x0 0x1000>;
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interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
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clock-names = "spiclk", "apb_pclk";
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dmas = <&dmac 8>, <&dmac 9>;
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dma-names = "tx", "rx";
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pinctrl-names = "default";
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pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>;
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status = "disabled";
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};
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wdt: watchdog@ff1a0000 {
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compatible = "snps,dw-wdt";
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reg = <0x0 0xff1a0000 0x0 0x100>;
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interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
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};
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saradc: adc@ff280000 {
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compatible = "rockchip,rk3328-saradc", "rockchip,rk3399-saradc";
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reg = <0x0 0xff280000 0x0 0x100>;
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interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
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#io-channel-cells = <1>;
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clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
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clock-names = "saradc", "apb_pclk";
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resets = <&cru SRST_SARADC_P>;
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reset-names = "saradc-apb";
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status = "disabled";
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};
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cru: clock-controller@ff440000 {
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compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
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reg = <0x0 0xff440000 0x0 0x1000>;
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rockchip,grf = <&grf>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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assigned-clocks =
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/*
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* CPLL should run at 1200, but that is to high for
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* the initial dividers of most of its children.
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* We need set cpll child clk div first,
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* and then set the cpll frequency.
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*/
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<&cru DCLK_LCDC>, <&cru SCLK_PDM>,
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<&cru SCLK_RTC32K>, <&cru SCLK_UART0>,
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<&cru SCLK_UART1>, <&cru SCLK_UART2>,
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<&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
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<&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>,
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<&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
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<&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
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<&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
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<&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
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<&cru SCLK_SDIO>, <&cru SCLK_TSP>,
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<&cru SCLK_WIFI>, <&cru ARMCLK>,
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<&cru PLL_GPLL>, <&cru PLL_CPLL>,
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<&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>,
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<&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
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<&cru HCLK_PERI>, <&cru PCLK_PERI>,
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<&cru SCLK_RTC32K>;
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assigned-clock-parents =
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<&cru HDMIPHY>, <&cru PLL_APLL>,
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<&cru PLL_GPLL>, <&xin24m>,
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<&xin24m>, <&xin24m>;
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assigned-clock-rates =
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<0>, <61440000>,
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<0>, <24000000>,
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<24000000>, <24000000>,
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<15000000>, <15000000>,
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<100000000>, <100000000>,
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<100000000>, <100000000>,
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<50000000>, <100000000>,
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<100000000>, <100000000>,
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<50000000>, <50000000>,
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<50000000>, <50000000>,
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<24000000>, <600000000>,
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<491520000>, <1200000000>,
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<150000000>, <75000000>,
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<75000000>, <150000000>,
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<75000000>, <75000000>,
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<32768>;
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};
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sdmmc: dwmmc@ff500000 {
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compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
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reg = <0x0 0xff500000 0x0 0x4000>;
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interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
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<&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
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clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
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fifo-depth = <0x100>;
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status = "disabled";
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};
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sdio: dwmmc@ff510000 {
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compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
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reg = <0x0 0xff510000 0x0 0x4000>;
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interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
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<&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
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clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
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fifo-depth = <0x100>;
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status = "disabled";
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};
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emmc: dwmmc@ff520000 {
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compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
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reg = <0x0 0xff520000 0x0 0x4000>;
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interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
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<&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
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clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
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fifo-depth = <0x100>;
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status = "disabled";
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};
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gmac2io: ethernet@ff540000 {
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compatible = "rockchip,rk3328-gmac";
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reg = <0x0 0xff540000 0x0 0x10000>;
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interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "macirq";
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clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>,
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<&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>,
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<&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>,
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<&cru PCLK_MAC2IO>;
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clock-names = "stmmaceth", "mac_clk_rx",
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"mac_clk_tx", "clk_mac_ref",
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"clk_mac_refout", "aclk_mac",
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"pclk_mac";
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resets = <&cru SRST_GMAC2IO_A>;
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reset-names = "stmmaceth";
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rockchip,grf = <&grf>;
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status = "disabled";
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};
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gic: interrupt-controller@ff811000 {
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compatible = "arm,gic-400";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0x0 0xff811000 0 0x1000>,
|
|
<0x0 0xff812000 0 0x2000>,
|
|
<0x0 0xff814000 0 0x2000>,
|
|
<0x0 0xff816000 0 0x2000>;
|
|
interrupts = <GIC_PPI 9
|
|
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
|
|
};
|
|
|
|
pinctrl: pinctrl {
|
|
compatible = "rockchip,rk3328-pinctrl";
|
|
rockchip,grf = <&grf>;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
|
|
gpio0: gpio0@ff210000 {
|
|
compatible = "rockchip,gpio-bank";
|
|
reg = <0x0 0xff210000 0x0 0x100>;
|
|
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru PCLK_GPIO0>;
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio1: gpio1@ff220000 {
|
|
compatible = "rockchip,gpio-bank";
|
|
reg = <0x0 0xff220000 0x0 0x100>;
|
|
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru PCLK_GPIO1>;
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio2: gpio2@ff230000 {
|
|
compatible = "rockchip,gpio-bank";
|
|
reg = <0x0 0xff230000 0x0 0x100>;
|
|
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru PCLK_GPIO2>;
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio3: gpio3@ff240000 {
|
|
compatible = "rockchip,gpio-bank";
|
|
reg = <0x0 0xff240000 0x0 0x100>;
|
|
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru PCLK_GPIO3>;
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
pcfg_pull_up: pcfg-pull-up {
|
|
bias-pull-up;
|
|
};
|
|
|
|
pcfg_pull_down: pcfg-pull-down {
|
|
bias-pull-down;
|
|
};
|
|
|
|
pcfg_pull_none: pcfg-pull-none {
|
|
bias-disable;
|
|
};
|
|
|
|
pcfg_pull_none_2ma: pcfg-pull-none-2ma {
|
|
bias-disable;
|
|
drive-strength = <2>;
|
|
};
|
|
|
|
pcfg_pull_up_2ma: pcfg-pull-up-2ma {
|
|
bias-pull-up;
|
|
drive-strength = <2>;
|
|
};
|
|
|
|
pcfg_pull_up_4ma: pcfg-pull-up-4ma {
|
|
bias-pull-up;
|
|
drive-strength = <4>;
|
|
};
|
|
|
|
pcfg_pull_none_4ma: pcfg-pull-none-4ma {
|
|
bias-disable;
|
|
drive-strength = <4>;
|
|
};
|
|
|
|
pcfg_pull_down_4ma: pcfg-pull-down-4ma {
|
|
bias-pull-down;
|
|
drive-strength = <4>;
|
|
};
|
|
|
|
pcfg_pull_none_8ma: pcfg-pull-none-8ma {
|
|
bias-disable;
|
|
drive-strength = <8>;
|
|
};
|
|
|
|
pcfg_pull_up_8ma: pcfg-pull-up-8ma {
|
|
bias-pull-up;
|
|
drive-strength = <8>;
|
|
};
|
|
|
|
pcfg_pull_none_12ma: pcfg-pull-none-12ma {
|
|
bias-disable;
|
|
drive-strength = <12>;
|
|
};
|
|
|
|
pcfg_pull_up_12ma: pcfg-pull-up-12ma {
|
|
bias-pull-up;
|
|
drive-strength = <12>;
|
|
};
|
|
|
|
pcfg_output_high: pcfg-output-high {
|
|
output-high;
|
|
};
|
|
|
|
pcfg_output_low: pcfg-output-low {
|
|
output-low;
|
|
};
|
|
|
|
pcfg_input_high: pcfg-input-high {
|
|
bias-pull-up;
|
|
input-enable;
|
|
};
|
|
|
|
pcfg_input: pcfg-input {
|
|
input-enable;
|
|
};
|
|
|
|
i2c0 {
|
|
i2c0_xfer: i2c0-xfer {
|
|
rockchip,pins = <2 RK_PD0 1 &pcfg_pull_none>,
|
|
<2 RK_PD1 1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
i2c1 {
|
|
i2c1_xfer: i2c1-xfer {
|
|
rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>,
|
|
<2 RK_PA5 2 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
i2c2 {
|
|
i2c2_xfer: i2c2-xfer {
|
|
rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>,
|
|
<2 RK_PB6 1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
i2c3 {
|
|
i2c3_xfer: i2c3-xfer {
|
|
rockchip,pins = <0 RK_PA5 2 &pcfg_pull_none>,
|
|
<0 RK_PA6 2 &pcfg_pull_none>;
|
|
};
|
|
i2c3_gpio: i2c3-gpio {
|
|
rockchip,pins =
|
|
<0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>,
|
|
<0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
hdmi_i2c {
|
|
hdmii2c_xfer: hdmii2c-xfer {
|
|
rockchip,pins = <0 RK_PA5 1 &pcfg_pull_none>,
|
|
<0 RK_PA6 1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
tsadc {
|
|
otp_gpio: otp-gpio {
|
|
rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
};
|
|
|
|
otp_out: otp-out {
|
|
rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
uart0 {
|
|
uart0_xfer: uart0-xfer {
|
|
rockchip,pins = <1 RK_PB1 1 &pcfg_pull_up>,
|
|
<1 RK_PB0 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
uart0_cts: uart0-cts {
|
|
rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
uart0_rts: uart0-rts {
|
|
rockchip,pins = <1 RK_PB2 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
uart0_rts_gpio: uart0-rts-gpio {
|
|
rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
uart1 {
|
|
uart1_xfer: uart1-xfer {
|
|
rockchip,pins = <3 RK_PA4 4 &pcfg_pull_up>,
|
|
<3 RK_PA6 4 &pcfg_pull_none>;
|
|
};
|
|
|
|
uart1_cts: uart1-cts {
|
|
rockchip,pins = <3 RK_PA7 4 &pcfg_pull_none>;
|
|
};
|
|
|
|
uart1_rts: uart1-rts {
|
|
rockchip,pins = <3 RK_PA5 4 &pcfg_pull_none>;
|
|
};
|
|
|
|
uart1_rts_gpio: uart1-rts-gpio {
|
|
rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
uart2-0 {
|
|
uart2m0_xfer: uart2m0-xfer {
|
|
rockchip,pins = <1 RK_PA0 2 &pcfg_pull_up>,
|
|
<1 RK_PA1 2 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
uart2-1 {
|
|
uart2m1_xfer: uart2m1-xfer {
|
|
rockchip,pins = <2 RK_PA0 1 &pcfg_pull_up>,
|
|
<2 RK_PA1 1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
spi0-0 {
|
|
spi0m0_clk: spi0m0-clk {
|
|
rockchip,pins = <2 RK_PB0 1 &pcfg_pull_up>;
|
|
};
|
|
|
|
spi0m0_cs0: spi0m0-cs0 {
|
|
rockchip,pins = <2 RK_PB3 1 &pcfg_pull_up>;
|
|
};
|
|
|
|
spi0m0_tx: spi0m0-tx {
|
|
rockchip,pins = <2 RK_PB1 1 &pcfg_pull_up>;
|
|
};
|
|
|
|
spi0m0_rx: spi0m0-rx {
|
|
rockchip,pins = <2 RK_PB2 1 &pcfg_pull_up>;
|
|
};
|
|
|
|
spi0m0_cs1: spi0m0-cs1 {
|
|
rockchip,pins = <2 RK_PB4 1 &pcfg_pull_up>;
|
|
};
|
|
};
|
|
|
|
spi0-1 {
|
|
spi0m1_clk: spi0m1-clk {
|
|
rockchip,pins = <3 RK_PC7 2 &pcfg_pull_up>;
|
|
};
|
|
|
|
spi0m1_cs0: spi0m1-cs0 {
|
|
rockchip,pins = <3 RK_PD2 2 &pcfg_pull_up>;
|
|
};
|
|
|
|
spi0m1_tx: spi0m1-tx {
|
|
rockchip,pins = <3 RK_PD1 2 &pcfg_pull_up>;
|
|
};
|
|
|
|
spi0m1_rx: spi0m1-rx {
|
|
rockchip,pins = <3 RK_PD0 2 &pcfg_pull_up>;
|
|
};
|
|
|
|
spi0m1_cs1: spi0m1-cs1 {
|
|
rockchip,pins = <3 RK_PD3 2 &pcfg_pull_up>;
|
|
};
|
|
};
|
|
|
|
spi0-2 {
|
|
spi0m2_clk: spi0m2-clk {
|
|
rockchip,pins = <3 RK_PA0 4 &pcfg_pull_up>;
|
|
};
|
|
|
|
spi0m2_cs0: spi0m2-cs0 {
|
|
rockchip,pins = <3 RK_PB0 3 &pcfg_pull_up>;
|
|
};
|
|
|
|
spi0m2_tx: spi0m2-tx {
|
|
rockchip,pins = <3 RK_PA1 4 &pcfg_pull_up>;
|
|
};
|
|
|
|
spi0m2_rx: spi0m2-rx {
|
|
rockchip,pins = <3 RK_PA2 4 &pcfg_pull_up>;
|
|
};
|
|
};
|
|
|
|
i2s1 {
|
|
i2s1_mclk: i2s1-mclk {
|
|
rockchip,pins = <2 RK_PB7 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
i2s1_sclk: i2s1-sclk {
|
|
rockchip,pins = <2 RK_PC2 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
i2s1_lrckrx: i2s1-lrckrx {
|
|
rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
i2s1_lrcktx: i2s1-lrcktx {
|
|
rockchip,pins = <2 RK_PC1 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
i2s1_sdi: i2s1-sdi {
|
|
rockchip,pins = <2 RK_PC3 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
i2s1_sdo: i2s1-sdo {
|
|
rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
i2s1_sdio1: i2s1-sdio1 {
|
|
rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
i2s1_sdio2: i2s1-sdio2 {
|
|
rockchip,pins = <2 RK_PC5 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
i2s1_sdio3: i2s1-sdio3 {
|
|
rockchip,pins = <2 RK_PC6 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
i2s1_sleep: i2s1-sleep {
|
|
rockchip,pins =
|
|
<2 RK_PB7 RK_FUNC_GPIO &pcfg_input_high>,
|
|
<2 RK_PC0 RK_FUNC_GPIO &pcfg_input_high>,
|
|
<2 RK_PC1 RK_FUNC_GPIO &pcfg_input_high>,
|
|
<2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>,
|
|
<2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>,
|
|
<2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>,
|
|
<2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
|
|
<2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>,
|
|
<2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
|
|
};
|
|
};
|
|
|
|
i2s2-0 {
|
|
i2s2m0_mclk: i2s2m0-mclk {
|
|
rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
i2s2m0_sclk: i2s2m0-sclk {
|
|
rockchip,pins = <1 RK_PC6 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
i2s2m0_lrckrx: i2s2m0-lrckrx {
|
|
rockchip,pins = <1 RK_PD2 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
i2s2m0_lrcktx: i2s2m0-lrcktx {
|
|
rockchip,pins = <1 RK_PC7 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
i2s2m0_sdi: i2s2m0-sdi {
|
|
rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
i2s2m0_sdo: i2s2m0-sdo {
|
|
rockchip,pins = <1 RK_PD1 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
i2s2m0_sleep: i2s2m0-sleep {
|
|
rockchip,pins =
|
|
<1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
|
|
<1 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>,
|
|
<1 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>,
|
|
<1 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>,
|
|
<1 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>,
|
|
<1 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>;
|
|
};
|
|
};
|
|
|
|
i2s2-1 {
|
|
i2s2m1_mclk: i2s2m1-mclk {
|
|
rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
i2s2m1_sclk: i2s2m1-sclk {
|
|
rockchip,pins = <3 RK_PA0 6 &pcfg_pull_none>;
|
|
};
|
|
|
|
i2s2m1_lrckrx: i2sm1-lrckrx {
|
|
rockchip,pins = <3 RK_PB0 6 &pcfg_pull_none>;
|
|
};
|
|
|
|
i2s2m1_lrcktx: i2s2m1-lrcktx {
|
|
rockchip,pins = <3 RK_PB0 4 &pcfg_pull_none>;
|
|
};
|
|
|
|
i2s2m1_sdi: i2s2m1-sdi {
|
|
rockchip,pins = <3 RK_PA2 6 &pcfg_pull_none>;
|
|
};
|
|
|
|
i2s2m1_sdo: i2s2m1-sdo {
|
|
rockchip,pins = <3 RK_PA1 6 &pcfg_pull_none>;
|
|
};
|
|
|
|
i2s2m1_sleep: i2s2m1-sleep {
|
|
rockchip,pins =
|
|
<1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
|
|
<3 RK_PA0 RK_FUNC_GPIO &pcfg_input_high>,
|
|
<3 RK_PB0 RK_FUNC_GPIO &pcfg_input_high>,
|
|
<3 RK_PA2 RK_FUNC_GPIO &pcfg_input_high>,
|
|
<3 RK_PA1 RK_FUNC_GPIO &pcfg_input_high>;
|
|
};
|
|
};
|
|
|
|
spdif-0 {
|
|
spdifm0_tx: spdifm0-tx {
|
|
rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
spdif-1 {
|
|
spdifm1_tx: spdifm1-tx {
|
|
rockchip,pins = <2 RK_PC1 2 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
spdif-2 {
|
|
spdifm2_tx: spdifm2-tx {
|
|
rockchip,pins = <0 RK_PA2 2 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
sdmmc0-0 {
|
|
sdmmc0m0_pwren: sdmmc0m0-pwren {
|
|
rockchip,pins = <2 RK_PA7 1 &pcfg_pull_up_4ma>;
|
|
};
|
|
|
|
sdmmc0m0_gpio: sdmmc0m0-gpio {
|
|
rockchip,pins = <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
|
|
};
|
|
};
|
|
|
|
sdmmc0-1 {
|
|
sdmmc0m1_pwren: sdmmc0m1-pwren {
|
|
rockchip,pins = <0 RK_PD6 3 &pcfg_pull_up_4ma>;
|
|
};
|
|
|
|
sdmmc0m1_gpio: sdmmc0m1-gpio {
|
|
rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
|
|
};
|
|
};
|
|
|
|
sdmmc0 {
|
|
sdmmc0_clk: sdmmc0-clk {
|
|
rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none_4ma>;
|
|
};
|
|
|
|
sdmmc0_cmd: sdmmc0-cmd {
|
|
rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up_4ma>;
|
|
};
|
|
|
|
sdmmc0_dectn: sdmmc0-dectn {
|
|
rockchip,pins = <1 RK_PA5 1 &pcfg_pull_up_4ma>;
|
|
};
|
|
|
|
sdmmc0_wrprt: sdmmc0-wrprt {
|
|
rockchip,pins = <1 RK_PA7 1 &pcfg_pull_up_4ma>;
|
|
};
|
|
|
|
sdmmc0_bus1: sdmmc0-bus1 {
|
|
rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_4ma>;
|
|
};
|
|
|
|
sdmmc0_bus4: sdmmc0-bus4 {
|
|
rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_4ma>,
|
|
<1 RK_PA1 1 &pcfg_pull_up_4ma>,
|
|
<1 RK_PA2 1 &pcfg_pull_up_4ma>,
|
|
<1 RK_PA3 1 &pcfg_pull_up_4ma>;
|
|
};
|
|
|
|
sdmmc0_gpio: sdmmc0-gpio {
|
|
rockchip,pins =
|
|
<1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
|
|
<1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
|
|
<1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
|
|
<1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
|
|
<1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
|
|
<1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
|
|
<1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
|
|
<1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
|
|
};
|
|
};
|
|
|
|
sdmmc0ext {
|
|
sdmmc0ext_clk: sdmmc0ext-clk {
|
|
rockchip,pins = <3 RK_PA2 3 &pcfg_pull_none_4ma>;
|
|
};
|
|
|
|
sdmmc0ext_cmd: sdmmc0ext-cmd {
|
|
rockchip,pins = <3 RK_PA0 3 &pcfg_pull_up_4ma>;
|
|
};
|
|
|
|
sdmmc0ext_wrprt: sdmmc0ext-wrprt {
|
|
rockchip,pins = <3 RK_PA3 3 &pcfg_pull_up_4ma>;
|
|
};
|
|
|
|
sdmmc0ext_dectn: sdmmc0ext-dectn {
|
|
rockchip,pins = <3 RK_PA1 3 &pcfg_pull_up_4ma>;
|
|
};
|
|
|
|
sdmmc0ext_bus1: sdmmc0ext-bus1 {
|
|
rockchip,pins = <3 RK_PA4 3 &pcfg_pull_up_4ma>;
|
|
};
|
|
|
|
sdmmc0ext_bus4: sdmmc0ext-bus4 {
|
|
rockchip,pins =
|
|
<3 RK_PA4 3 &pcfg_pull_up_4ma>,
|
|
<3 RK_PA5 3 &pcfg_pull_up_4ma>,
|
|
<3 RK_PA6 3 &pcfg_pull_up_4ma>,
|
|
<3 RK_PA7 3 &pcfg_pull_up_4ma>;
|
|
};
|
|
|
|
sdmmc0ext_gpio: sdmmc0ext-gpio {
|
|
rockchip,pins =
|
|
<3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
|
|
<3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
|
|
<3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
|
|
<3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
|
|
<3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
|
|
<3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
|
|
<3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
|
|
<3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
|
|
};
|
|
};
|
|
|
|
sdmmc1 {
|
|
sdmmc1_clk: sdmmc1-clk {
|
|
rockchip,pins = <1 RK_PB4 1 &pcfg_pull_none_8ma>;
|
|
};
|
|
|
|
sdmmc1_cmd: sdmmc1-cmd {
|
|
rockchip,pins = <1 RK_PB5 1 &pcfg_pull_up_8ma>;
|
|
};
|
|
|
|
sdmmc1_pwren: sdmmc1-pwren {
|
|
rockchip,pins = <1 RK_PC2 1 &pcfg_pull_up_8ma>;
|
|
};
|
|
|
|
sdmmc1_wrprt: sdmmc1-wrprt {
|
|
rockchip,pins = <1 RK_PC4 1 &pcfg_pull_up_8ma>;
|
|
};
|
|
|
|
sdmmc1_dectn: sdmmc1-dectn {
|
|
rockchip,pins = <1 RK_PC3 1 &pcfg_pull_up_8ma>;
|
|
};
|
|
|
|
sdmmc1_bus1: sdmmc1-bus1 {
|
|
rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>;
|
|
};
|
|
|
|
sdmmc1_bus4: sdmmc1-bus4 {
|
|
rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>,
|
|
<1 RK_PB7 1 &pcfg_pull_up_8ma>,
|
|
<1 RK_PC0 1 &pcfg_pull_up_8ma>,
|
|
<1 RK_PC1 1 &pcfg_pull_up_8ma>;
|
|
};
|
|
|
|
sdmmc1_gpio: sdmmc1-gpio {
|
|
rockchip,pins =
|
|
<1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
|
|
<1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
|
|
<1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
|
|
<1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
|
|
<1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
|
|
<1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
|
|
<1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
|
|
<1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
|
|
<1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
|
|
};
|
|
};
|
|
|
|
emmc {
|
|
emmc_clk: emmc-clk {
|
|
rockchip,pins = <3 RK_PC5 2 &pcfg_pull_none_12ma>;
|
|
};
|
|
|
|
emmc_cmd: emmc-cmd {
|
|
rockchip,pins = <3 RK_PC3 2 &pcfg_pull_up_12ma>;
|
|
};
|
|
|
|
emmc_pwren: emmc-pwren {
|
|
rockchip,pins = <3 RK_PC6 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
emmc_rstnout: emmc-rstnout {
|
|
rockchip,pins = <3 RK_PC4 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
emmc_bus1: emmc-bus1 {
|
|
rockchip,pins = <0 RK_PA7 2 &pcfg_pull_up_12ma>;
|
|
};
|
|
|
|
emmc_bus4: emmc-bus4 {
|
|
rockchip,pins =
|
|
<0 RK_PA7 2 &pcfg_pull_up_12ma>,
|
|
<2 RK_PD4 2 &pcfg_pull_up_12ma>,
|
|
<2 RK_PD5 2 &pcfg_pull_up_12ma>,
|
|
<2 RK_PD6 2 &pcfg_pull_up_12ma>;
|
|
};
|
|
|
|
emmc_bus8: emmc-bus8 {
|
|
rockchip,pins =
|
|
<0 RK_PA7 2 &pcfg_pull_up_12ma>,
|
|
<2 RK_PD4 2 &pcfg_pull_up_12ma>,
|
|
<2 RK_PD5 2 &pcfg_pull_up_12ma>,
|
|
<2 RK_PD6 2 &pcfg_pull_up_12ma>,
|
|
<2 RK_PD7 2 &pcfg_pull_up_12ma>,
|
|
<3 RK_PC0 2 &pcfg_pull_up_12ma>,
|
|
<3 RK_PC1 2 &pcfg_pull_up_12ma>,
|
|
<3 RK_PC2 2 &pcfg_pull_up_12ma>;
|
|
};
|
|
};
|
|
|
|
pwm0 {
|
|
pwm0_pin: pwm0-pin {
|
|
rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
pwm1 {
|
|
pwm1_pin: pwm1-pin {
|
|
rockchip,pins = <2 RK_PA5 1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
pwm2 {
|
|
pwm2_pin: pwm2-pin {
|
|
rockchip,pins = <2 RK_PA6 1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
pwmir {
|
|
pwmir_pin: pwmir-pin {
|
|
rockchip,pins = <2 RK_PA2 1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
gmac-1 {
|
|
rgmiim1_pins: rgmiim1-pins {
|
|
rockchip,pins =
|
|
/* mac_txclk */
|
|
<1 RK_PB4 2 &pcfg_pull_none_12ma>,
|
|
/* mac_rxclk */
|
|
<1 RK_PB5 2 &pcfg_pull_none_2ma>,
|
|
/* mac_mdio */
|
|
<1 RK_PC3 2 &pcfg_pull_none_2ma>,
|
|
/* mac_txen */
|
|
<1 RK_PD1 2 &pcfg_pull_none_12ma>,
|
|
/* mac_clk */
|
|
<1 RK_PC5 2 &pcfg_pull_none_2ma>,
|
|
/* mac_rxdv */
|
|
<1 RK_PC6 2 &pcfg_pull_none_2ma>,
|
|
/* mac_mdc */
|
|
<1 RK_PC7 2 &pcfg_pull_none_2ma>,
|
|
/* mac_rxd1 */
|
|
<1 RK_PB2 2 &pcfg_pull_none_2ma>,
|
|
/* mac_rxd0 */
|
|
<1 RK_PB3 2 &pcfg_pull_none_2ma>,
|
|
/* mac_txd1 */
|
|
<1 RK_PB0 2 &pcfg_pull_none_12ma>,
|
|
/* mac_txd0 */
|
|
<1 RK_PB1 2 &pcfg_pull_none_12ma>,
|
|
/* mac_rxd3 */
|
|
<1 RK_PB6 2 &pcfg_pull_none_2ma>,
|
|
/* mac_rxd2 */
|
|
<1 RK_PB7 2 &pcfg_pull_none_2ma>,
|
|
/* mac_txd3 */
|
|
<1 RK_PC0 2 &pcfg_pull_none_12ma>,
|
|
/* mac_txd2 */
|
|
<1 RK_PC1 2 &pcfg_pull_none_12ma>,
|
|
|
|
/* mac_txclk */
|
|
<0 RK_PB0 1 &pcfg_pull_none>,
|
|
/* mac_txen */
|
|
<0 RK_PB4 1 &pcfg_pull_none>,
|
|
/* mac_clk */
|
|
<0 RK_PD0 1 &pcfg_pull_none>,
|
|
/* mac_txd1 */
|
|
<0 RK_PC0 1 &pcfg_pull_none>,
|
|
/* mac_txd0 */
|
|
<0 RK_PC1 1 &pcfg_pull_none>,
|
|
/* mac_txd3 */
|
|
<0 RK_PC7 1 &pcfg_pull_none>,
|
|
/* mac_txd2 */
|
|
<0 RK_PC6 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
rmiim1_pins: rmiim1-pins {
|
|
rockchip,pins =
|
|
/* mac_mdio */
|
|
<1 RK_PC3 2 &pcfg_pull_none_2ma>,
|
|
/* mac_txen */
|
|
<1 RK_PD1 2 &pcfg_pull_none_12ma>,
|
|
/* mac_clk */
|
|
<1 RK_PC5 2 &pcfg_pull_none_2ma>,
|
|
/* mac_rxer */
|
|
<1 RK_PD0 2 &pcfg_pull_none_2ma>,
|
|
/* mac_rxdv */
|
|
<1 RK_PC6 2 &pcfg_pull_none_2ma>,
|
|
/* mac_mdc */
|
|
<1 RK_PC7 2 &pcfg_pull_none_2ma>,
|
|
/* mac_rxd1 */
|
|
<1 RK_PB2 2 &pcfg_pull_none_2ma>,
|
|
/* mac_rxd0 */
|
|
<1 RK_PB3 2 &pcfg_pull_none_2ma>,
|
|
/* mac_txd1 */
|
|
<1 RK_PB0 2 &pcfg_pull_none_12ma>,
|
|
/* mac_txd0 */
|
|
<1 RK_PB1 2 &pcfg_pull_none_12ma>,
|
|
|
|
/* mac_mdio */
|
|
<0 RK_PB3 1 &pcfg_pull_none>,
|
|
/* mac_txen */
|
|
<0 RK_PB4 1 &pcfg_pull_none>,
|
|
/* mac_clk */
|
|
<0 RK_PD0 1 &pcfg_pull_none>,
|
|
/* mac_mdc */
|
|
<0 RK_PC3 1 &pcfg_pull_none>,
|
|
/* mac_txd1 */
|
|
<0 RK_PC0 1 &pcfg_pull_none>,
|
|
/* mac_txd0 */
|
|
<0 RK_PC1 1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
gmac2phy {
|
|
fephyled_speed100: fephyled-speed100 {
|
|
rockchip,pins = <0 RK_PD7 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
fephyled_speed10: fephyled-speed10 {
|
|
rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
fephyled_duplex: fephyled-duplex {
|
|
rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
fephyled_rxm0: fephyled-rxm0 {
|
|
rockchip,pins = <0 RK_PD5 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
fephyled_txm0: fephyled-txm0 {
|
|
rockchip,pins = <0 RK_PD5 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
fephyled_linkm0: fephyled-linkm0 {
|
|
rockchip,pins = <0 RK_PD4 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
fephyled_rxm1: fephyled-rxm1 {
|
|
rockchip,pins = <2 RK_PD1 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
fephyled_txm1: fephyled-txm1 {
|
|
rockchip,pins = <2 RK_PD1 3 &pcfg_pull_none>;
|
|
};
|
|
|
|
fephyled_linkm1: fephyled-linkm1 {
|
|
rockchip,pins = <2 RK_PD0 2 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
tsadc_pin {
|
|
tsadc_int: tsadc-int {
|
|
rockchip,pins = <2 RK_PB5 2 &pcfg_pull_none>;
|
|
};
|
|
tsadc_gpio: tsadc-gpio {
|
|
rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
hdmi_pin {
|
|
hdmi_cec: hdmi-cec {
|
|
rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
hdmi_hpd: hdmi-hpd {
|
|
rockchip,pins = <0 RK_PA4 1 &pcfg_pull_down>;
|
|
};
|
|
};
|
|
|
|
cif-0 {
|
|
dvp_d2d9_m0:dvp-d2d9-m0 {
|
|
rockchip,pins =
|
|
/* cif_d0 */
|
|
<3 RK_PA4 2 &pcfg_pull_none>,
|
|
/* cif_d1 */
|
|
<3 RK_PA5 2 &pcfg_pull_none>,
|
|
/* cif_d2 */
|
|
<3 RK_PA6 2 &pcfg_pull_none>,
|
|
/* cif_d3 */
|
|
<3 RK_PA7 2 &pcfg_pull_none>,
|
|
/* cif_d4 */
|
|
<3 RK_PB0 2 &pcfg_pull_none>,
|
|
/* cif_d5m0 */
|
|
<3 RK_PB1 2 &pcfg_pull_none>,
|
|
/* cif_d6m0 */
|
|
<3 RK_PB2 2 &pcfg_pull_none>,
|
|
/* cif_d7m0 */
|
|
<3 RK_PB3 2 &pcfg_pull_none>,
|
|
/* cif_href */
|
|
<3 RK_PA1 2 &pcfg_pull_none>,
|
|
/* cif_vsync */
|
|
<3 RK_PA0 2 &pcfg_pull_none>,
|
|
/* cif_clkoutm0 */
|
|
<3 RK_PA3 2 &pcfg_pull_none>,
|
|
/* cif_clkin */
|
|
<3 RK_PA2 2 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
cif-1 {
|
|
dvp_d2d9_m1:dvp-d2d9-m1 {
|
|
rockchip,pins =
|
|
/* cif_d0 */
|
|
<3 RK_PA4 2 &pcfg_pull_none>,
|
|
/* cif_d1 */
|
|
<3 RK_PA5 2 &pcfg_pull_none>,
|
|
/* cif_d2 */
|
|
<3 RK_PA6 2 &pcfg_pull_none>,
|
|
/* cif_d3 */
|
|
<3 RK_PA7 2 &pcfg_pull_none>,
|
|
/* cif_d4 */
|
|
<3 RK_PB0 2 &pcfg_pull_none>,
|
|
/* cif_d5m1 */
|
|
<2 RK_PC0 4 &pcfg_pull_none>,
|
|
/* cif_d6m1 */
|
|
<2 RK_PC1 4 &pcfg_pull_none>,
|
|
/* cif_d7m1 */
|
|
<2 RK_PC2 4 &pcfg_pull_none>,
|
|
/* cif_href */
|
|
<3 RK_PA1 2 &pcfg_pull_none>,
|
|
/* cif_vsync */
|
|
<3 RK_PA0 2 &pcfg_pull_none>,
|
|
/* cif_clkoutm1 */
|
|
<2 RK_PB7 4 &pcfg_pull_none>,
|
|
/* cif_clkin */
|
|
<3 RK_PA2 2 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
};
|
|
};
|