forked from Minki/linux
2b29ca22ed
As I found by chance while merging another patch, the usage of a dma-mask in this DT node is wrong for multiple reasons: - dma-masks are a Linux specific concept, not a general hardware feature - In DT, we use the "dma-ranges" property to describe how DMA addresses related between devices. - The 40-bit mask appears to be completely unnecessary here, as the SoC cannot address that much memory anyway, so simply asking for a 64-bit mask (as supported by the device) should succeed anyway. The patch to remove the parsing of the property is getting merged through the crypto tree. Signed-off-by: Arnd Bergmann <arnd@arndb.de>
357 lines
9.9 KiB
Plaintext
357 lines
9.9 KiB
Plaintext
/*
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* Copyright (C) 2016 Marvell Technology Group Ltd.
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPLv2 or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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/*
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* Device Tree file for Marvell Armada CP110 Master.
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*/
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#define ICU_GRP_NSR 0x0
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/ {
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cp110-master {
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "simple-bus";
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interrupt-parent = <&cpm_icu>;
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ranges;
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config-space@f2000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges = <0x0 0x0 0xf2000000 0x2000000>;
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cpm_ethernet: ethernet@0 {
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compatible = "marvell,armada-7k-pp22";
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reg = <0x0 0x100000>, <0x129000 0xb000>;
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clocks = <&cpm_clk 1 3>, <&cpm_clk 1 9>, <&cpm_clk 1 5>;
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clock-names = "pp_clk", "gop_clk", "mg_clk";
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status = "disabled";
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dma-coherent;
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cpm_eth0: eth0 {
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interrupts = <ICU_GRP_NSR 39 IRQ_TYPE_LEVEL_HIGH>;
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port-id = <0>;
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gop-port-id = <0>;
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status = "disabled";
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};
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cpm_eth1: eth1 {
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interrupts = <ICU_GRP_NSR 40 IRQ_TYPE_LEVEL_HIGH>;
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port-id = <1>;
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gop-port-id = <2>;
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status = "disabled";
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};
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cpm_eth2: eth2 {
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interrupts = <ICU_GRP_NSR 41 IRQ_TYPE_LEVEL_HIGH>;
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port-id = <2>;
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gop-port-id = <3>;
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status = "disabled";
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};
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};
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cpm_mdio: mdio@12a200 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "marvell,orion-mdio";
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reg = <0x12a200 0x10>;
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clocks = <&cpm_clk 1 9>, <&cpm_clk 1 5>;
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status = "disabled";
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};
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cpm_xmdio: mdio@12a600 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "marvell,xmdio";
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reg = <0x12a600 0x10>;
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status = "disabled";
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};
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cpm_icu: interrupt-controller@1e0000 {
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compatible = "marvell,cp110-icu";
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reg = <0x1e0000 0x10>;
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#interrupt-cells = <3>;
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interrupt-controller;
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msi-parent = <&gicp>;
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};
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cpm_syscon0: system-controller@440000 {
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compatible = "syscon", "simple-mfd";
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reg = <0x440000 0x1000>;
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cpm_clk: clock {
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compatible = "marvell,cp110-clock";
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#clock-cells = <2>;
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};
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cpm_gpio1: gpio@100 {
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compatible = "marvell,armada-8k-gpio";
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offset = <0x100>;
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ngpios = <32>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&cpm_pinctrl 0 0 32>;
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status = "disabled";
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};
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cpm_gpio2: gpio@140 {
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compatible = "marvell,armada-8k-gpio";
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offset = <0x140>;
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ngpios = <31>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&cpm_pinctrl 0 32 31>;
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status = "disabled";
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};
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};
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cpm_rtc: rtc@284000 {
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compatible = "marvell,armada-8k-rtc";
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reg = <0x284000 0x20>, <0x284080 0x24>;
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reg-names = "rtc", "rtc-soc";
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interrupts = <ICU_GRP_NSR 77 IRQ_TYPE_LEVEL_HIGH>;
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};
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cpm_sata0: sata@540000 {
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compatible = "marvell,armada-8k-ahci",
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"generic-ahci";
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reg = <0x540000 0x30000>;
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interrupts = <ICU_GRP_NSR 107 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpm_clk 1 15>;
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status = "disabled";
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};
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cpm_usb3_0: usb3@500000 {
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compatible = "marvell,armada-8k-xhci",
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"generic-xhci";
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reg = <0x500000 0x4000>;
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dma-coherent;
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interrupts = <ICU_GRP_NSR 106 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpm_clk 1 22>;
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status = "disabled";
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};
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cpm_usb3_1: usb3@510000 {
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compatible = "marvell,armada-8k-xhci",
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"generic-xhci";
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reg = <0x510000 0x4000>;
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dma-coherent;
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interrupts = <ICU_GRP_NSR 105 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpm_clk 1 23>;
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status = "disabled";
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};
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cpm_xor0: xor@6a0000 {
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compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
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reg = <0x6a0000 0x1000>,
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<0x6b0000 0x1000>;
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dma-coherent;
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msi-parent = <&gic_v2m0>;
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clocks = <&cpm_clk 1 8>;
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};
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cpm_xor1: xor@6c0000 {
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compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
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reg = <0x6c0000 0x1000>,
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<0x6d0000 0x1000>;
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dma-coherent;
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msi-parent = <&gic_v2m0>;
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clocks = <&cpm_clk 1 7>;
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};
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cpm_spi0: spi@700600 {
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compatible = "marvell,armada-380-spi";
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reg = <0x700600 0x50>;
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#address-cells = <0x1>;
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#size-cells = <0x0>;
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cell-index = <1>;
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clocks = <&cpm_clk 1 21>;
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status = "disabled";
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};
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cpm_spi1: spi@700680 {
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compatible = "marvell,armada-380-spi";
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reg = <0x700680 0x50>;
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <2>;
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clocks = <&cpm_clk 1 21>;
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status = "disabled";
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};
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cpm_i2c0: i2c@701000 {
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compatible = "marvell,mv78230-i2c";
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reg = <0x701000 0x20>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <ICU_GRP_NSR 120 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpm_clk 1 21>;
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status = "disabled";
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};
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cpm_i2c1: i2c@701100 {
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compatible = "marvell,mv78230-i2c";
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reg = <0x701100 0x20>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <ICU_GRP_NSR 121 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpm_clk 1 21>;
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status = "disabled";
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};
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cpm_trng: trng@760000 {
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compatible = "marvell,armada-8k-rng", "inside-secure,safexcel-eip76";
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reg = <0x760000 0x7d>;
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interrupts = <ICU_GRP_NSR 95 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpm_clk 1 25>;
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status = "okay";
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};
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cpm_sdhci0: sdhci@780000 {
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compatible = "marvell,armada-cp110-sdhci";
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reg = <0x780000 0x300>;
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interrupts = <ICU_GRP_NSR 27 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "core";
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clocks = <&cpm_clk 1 4>;
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dma-coherent;
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status = "disabled";
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};
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cpm_crypto: crypto@800000 {
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compatible = "inside-secure,safexcel-eip197";
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reg = <0x800000 0x200000>;
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interrupts = <ICU_GRP_NSR 87 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 88 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 89 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 90 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 91 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 92 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "mem", "ring0", "ring1",
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"ring2", "ring3", "eip";
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clocks = <&cpm_clk 1 26>;
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};
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};
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cpm_pcie0: pcie@f2600000 {
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compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
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reg = <0 0xf2600000 0 0x10000>,
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<0 0xf6f00000 0 0x80000>;
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reg-names = "ctrl", "config";
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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device_type = "pci";
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dma-coherent;
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msi-parent = <&gic_v2m0>;
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bus-range = <0 0xff>;
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ranges =
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/* downstream I/O */
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<0x81000000 0 0xf9000000 0 0xf9000000 0 0x10000
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/* non-prefetchable memory */
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0x82000000 0 0xf6000000 0 0xf6000000 0 0xf00000>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &cpm_icu 0 ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
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num-lanes = <1>;
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clocks = <&cpm_clk 1 13>;
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status = "disabled";
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};
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cpm_pcie1: pcie@f2620000 {
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compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
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reg = <0 0xf2620000 0 0x10000>,
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<0 0xf7f00000 0 0x80000>;
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reg-names = "ctrl", "config";
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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device_type = "pci";
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dma-coherent;
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msi-parent = <&gic_v2m0>;
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bus-range = <0 0xff>;
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ranges =
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/* downstream I/O */
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<0x81000000 0 0xf9010000 0 0xf9010000 0 0x10000
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/* non-prefetchable memory */
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0x82000000 0 0xf7000000 0 0xf7000000 0 0xf00000>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &cpm_icu 0 ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
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num-lanes = <1>;
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clocks = <&cpm_clk 1 11>;
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status = "disabled";
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};
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cpm_pcie2: pcie@f2640000 {
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compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
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reg = <0 0xf2640000 0 0x10000>,
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<0 0xf8f00000 0 0x80000>;
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reg-names = "ctrl", "config";
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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device_type = "pci";
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dma-coherent;
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msi-parent = <&gic_v2m0>;
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bus-range = <0 0xff>;
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ranges =
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/* downstream I/O */
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<0x81000000 0 0xf9020000 0 0xf9020000 0 0x10000
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/* non-prefetchable memory */
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0x82000000 0 0xf8000000 0 0xf8000000 0 0xf00000>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &cpm_icu 0 ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
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num-lanes = <1>;
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clocks = <&cpm_clk 1 12>;
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status = "disabled";
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};
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};
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};
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