c96348a8fb
Handling of the interrupt callback lists is done in dpu_core_irq.c,
under the "cb_lock" spinlock. When these operations results in the need
for enableing or disabling the IRQ in the hardware the code jumps to
dpu_hw_interrupts.c, which protects its operations with "irq_lock"
spinlock.
When an interrupt fires, dpu_hw_intr_dispatch_irq() inspects the
hardware state while holding the "irq_lock" spinlock and jumps to
dpu_core_irq_callback_handler() to invoke the registered handlers, which
traverses the callback list under the "cb_lock" spinlock.
As such, in the event that these happens concurrently we'll end up with
a deadlock.
Prior to '1c1e7763a6d4 ("drm/msm/dpu: simplify IRQ enabling/disabling")'
the enable/disable of the hardware interrupt was done outside the
"cb_lock" region, optimitically by using an atomic enable-counter for
each interrupt and an warning print if someone changed the list between
the atomic_read and the time the operation concluded.
Rather than re-introducing the large array of atomics, this change
embraces the fact that dpu_core_irq and dpu_hw_interrupts are deeply
entangled and make them share the single "irq_lock".
Following this step it's suggested that we squash the two parts into a
single irq handling thing.
Fixes: 1c1e7763a6d4 ("drm/msm/dpu: simplify IRQ enabling/disabling")
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20210611170003.3539059-1-bjorn.andersson@linaro.org
Signed-off-by: Rob Clark <robdclark@chromium.org>
154 lines
4.0 KiB
C
154 lines
4.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
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*/
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#ifndef _DPU_HW_INTERRUPTS_H
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#define _DPU_HW_INTERRUPTS_H
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#include <linux/types.h>
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#include "dpu_hwio.h"
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#include "dpu_hw_catalog.h"
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#include "dpu_hw_util.h"
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#include "dpu_hw_mdss.h"
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/* When making changes be sure to sync with dpu_intr_set */
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enum dpu_hw_intr_reg {
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MDP_SSPP_TOP0_INTR,
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MDP_SSPP_TOP0_INTR2,
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MDP_SSPP_TOP0_HIST_INTR,
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MDP_INTF0_INTR,
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MDP_INTF1_INTR,
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MDP_INTF2_INTR,
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MDP_INTF3_INTR,
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MDP_INTF4_INTR,
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MDP_AD4_0_INTR,
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MDP_AD4_1_INTR,
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MDP_INTF0_7xxx_INTR,
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MDP_INTF1_7xxx_INTR,
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MDP_INTF5_7xxx_INTR,
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MDP_INTR_MAX,
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};
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#define DPU_IRQ_IDX(reg_idx, offset) (reg_idx * 32 + offset)
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struct dpu_hw_intr;
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/**
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* Interrupt operations.
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*/
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struct dpu_hw_intr_ops {
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/**
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* enable_irq - Enable IRQ based on lookup IRQ index
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* @intr: HW interrupt handle
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* @irq_idx: Lookup irq index return from irq_idx_lookup
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* @return: 0 for success, otherwise failure
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*/
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int (*enable_irq_locked)(
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struct dpu_hw_intr *intr,
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int irq_idx);
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/**
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* disable_irq - Disable IRQ based on lookup IRQ index
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* @intr: HW interrupt handle
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* @irq_idx: Lookup irq index return from irq_idx_lookup
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* @return: 0 for success, otherwise failure
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*/
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int (*disable_irq_locked)(
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struct dpu_hw_intr *intr,
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int irq_idx);
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/**
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* clear_all_irqs - Clears all the interrupts (i.e. acknowledges
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* any asserted IRQs). Useful during reset.
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* @intr: HW interrupt handle
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* @return: 0 for success, otherwise failure
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*/
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int (*clear_all_irqs)(
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struct dpu_hw_intr *intr);
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/**
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* disable_all_irqs - Disables all the interrupts. Useful during reset.
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* @intr: HW interrupt handle
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* @return: 0 for success, otherwise failure
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*/
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int (*disable_all_irqs)(
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struct dpu_hw_intr *intr);
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/**
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* dispatch_irqs - IRQ dispatcher will call the given callback
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* function when a matching interrupt status bit is
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* found in the irq mapping table.
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* @intr: HW interrupt handle
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* @cbfunc: Callback function pointer
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* @arg: Argument to pass back during callback
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*/
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void (*dispatch_irqs)(
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struct dpu_hw_intr *intr,
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void (*cbfunc)(void *arg, int irq_idx),
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void *arg);
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/**
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* get_interrupt_status - Gets HW interrupt status, and clear if set,
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* based on given lookup IRQ index.
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* @intr: HW interrupt handle
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* @irq_idx: Lookup irq index return from irq_idx_lookup
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* @clear: True to clear irq after read
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*/
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u32 (*get_interrupt_status)(
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struct dpu_hw_intr *intr,
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int irq_idx,
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bool clear);
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/**
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* lock - take the IRQ lock
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* @intr: HW interrupt handle
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* @return: irq_flags for the taken spinlock
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*/
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unsigned long (*lock)(
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struct dpu_hw_intr *intr);
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/**
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* unlock - take the IRQ lock
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* @intr: HW interrupt handle
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* @irq_flags: the irq_flags returned from lock
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*/
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void (*unlock)(
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struct dpu_hw_intr *intr, unsigned long irq_flags);
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};
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/**
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* struct dpu_hw_intr: hw interrupts handling data structure
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* @hw: virtual address mapping
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* @ops: function pointer mapping for IRQ handling
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* @cache_irq_mask: array of IRQ enable masks reg storage created during init
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* @save_irq_status: array of IRQ status reg storage created during init
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* @total_irqs: total number of irq_idx mapped in the hw_interrupts
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* @irq_lock: spinlock for accessing IRQ resources
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*/
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struct dpu_hw_intr {
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struct dpu_hw_blk_reg_map hw;
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struct dpu_hw_intr_ops ops;
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u32 *cache_irq_mask;
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u32 *save_irq_status;
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u32 total_irqs;
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spinlock_t irq_lock;
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unsigned long irq_mask;
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};
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/**
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* dpu_hw_intr_init(): Initializes the interrupts hw object
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* @addr: mapped register io address of MDP
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* @m : pointer to mdss catalog data
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*/
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struct dpu_hw_intr *dpu_hw_intr_init(void __iomem *addr,
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struct dpu_mdss_cfg *m);
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/**
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* dpu_hw_intr_destroy(): Cleanup interrutps hw object
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* @intr: pointer to interrupts hw object
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*/
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void dpu_hw_intr_destroy(struct dpu_hw_intr *intr);
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#endif
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